Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

Based on the quasi-two-dimensional(2D) solution of Poisson’s equation in two continuous channel regions, an analytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate(JLDMCSG) metal-oxide-semiconductor field-effect transistor(MOSFET) is developed. Using the derived model, channel potential distribution, horizontal electrical field distribution, and threshold voltage roll-off of JLDMCSG MOSFET are investigated. Compared with junctionless single-material CSG(JLSGCSG) MOSFET, JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage rolloff of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional(3D) numerical device simulator ISE.     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer

A novel ultralow turnoff loss dual-gate silicon-on-insulator(SOI) lateral insulated gate bipolar transistor(LIGBT) is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored(CS) layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the carrier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop(Von). In the off-state, due to the uniform carrier distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss(Eoff). Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoffand Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.     

绝缘体上硅金属氧化物半导体场效应晶体管中辐射导致的寄生效应研究

基于⁶⁰Co γ射线源研究了总剂量辐射对绝缘体上硅（silicon on insulator,SOI）金属氧化物半导体场效应晶体管器件的影响.通过对比不同尺寸器件的辐射响应,分析了导致辐照后器件性能退化的不同机制.实验表明：器件的性能退化来源于辐射增强的寄生效应;浅沟槽隔离（shallow trench isolation,STI）寄生晶体管的开启导致了关态漏电流随总剂量呈指数增加,直到达到饱和;STI氧化层的陷阱电荷共享导致了窄沟道器件的阈值电压漂移,而短沟道器件的阈值电压漂移则来自于背栅阈值耦合;在同一工艺下,尺寸较小的器件对总剂量效应更敏感.探讨了背栅和体区加负偏压对总剂量效应的影响,SOI器件背栅或体区的负偏压可以在一定程度上抑制辐射增强的寄生效应,从而改善辐照后器件的电学特性.     

高k栅介质应变Si SOI MOSFET的阈值电压解析模型

在结合应变Si,高k栅和SOI结构三者的优点的基础上,提出了一种新型的高k栅介质应变Si全耗尽SOI MOSFET结构.通过求解二维泊松方程建立了该新结构的二维阈值电压模型,在该模型中考虑了影响阈值电压的主要参数.分析了阈值电压与弛豫层中的Ge组分、应变Si层厚度的关系.研究结果表明阈值电压随弛豫层中Ge组分的提高和应变Si层的厚度增加而降低.此外,还分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系.研究结果表明阈值电压随高k介质的介 关键词： 应变Si k栅')" href="#">高k栅 短沟道效应 漏致势垒降低     

A new nanoscale and high temperature field effect transistor: Bi level FinFET

In this paper, we propose a new Bi Level Fin Field Effect Transistor (BL-FinFET) where the fin regions consist of Bi level. The novel features of the BL-FinFET are simulated and compared with a Conventional FinFET (C-FinFET). The three-dimensional and two-carrier device simulation demonstrate that the application of Bi level to the FinFET structure results in an ideal threshold voltage roll-off, reduced DIBL, excellent behavior in voltage gain at high temperatures and the gate capacitance improvement when compared with the C-FinFET. Also, this paper illustrates the benefits of the high performance BL-FinFET device over the conventional one and expands the application of Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (SOI MOSFETs) to high temperature.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

部分耗尽结构绝缘体上硅器件的低频噪声特性

针对部分耗尽结构绝缘体上硅(silicon-on-insulator, SOI)器件低频噪声特性展开实验与理论研究. 实验结果表明, 器件低频噪声主要来源于SiO₂-Si界面附近缺陷态对载流子的俘获与释放过程; 基于此理论可提取前栅和背栅氧化层界面附近缺陷态密度分别为8×10¹⁷ eV^-1·cm^-3和2.76×10¹⁷ eV^-1·cm^-3. 基于电荷隧穿机理, 在考虑隧穿削弱因子、隧穿距离与时间常数之间关系的基础上, 提取了前、背栅氧化层内缺陷态密度随空间的分布情况. 此外, SOI器件沟道电流归一化噪声功率谱密度随沟道长度的增加而线性减小, 这表明器件低频噪声主要来源于沟道的闪烁噪声. 最后, 基于电荷耦合效应, 分析了背栅电压对前栅阈值电压、沟道电流以及沟道电流噪声功率谱密度的影响.     

Electronic transport properties of silicon junctionless nanowire transistors fabricated by femtosecond laser direct writing

Silicon junctionless nanowire transistor(JNT) is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold swing(SS),and electron mobility are evaluated.The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K.The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to50 K,which is attributed to the electron transport through one-dimensional(1D) subbands formed in the nanowire.Besides,the device exhibits a better low-field electron mobility of 290 cm~2·V~(-1)·s~(-1),implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties.This approach provides a potential application for nanoscale device patterning.     

All optical NOR and NAND gate based on nonlinear photonic crystal ring resonators

In this paper we proposed optical NOR and NAND gates. By combining nonlinear Kerr effect with photonic crystal ring resonators first we designed a structure, whose optical behavior can be controlled via input power intensity. The switching power threshold obtained for this structure equal to 2 kW/μm². For designing the proposed optical logic gates we employed two resonant rings with the same structures, both rings at the logic gates were designed such that their resonant wavelength be at λ = 1550 nm. Every proposed logic gate has one bias and two logic input ports. We used plane wave expansion and finite difference time domain methods for analyzing the proposed structures.     

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.     

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

The present paper proposes a new Fin Field Effect Transistor (FinFET) with an amended Channel (AC). The fin region consists of two sections; the lower part which has a rounded shape and the upper part of fin as conventional FinFETs, is cubic. The AC-FinFET devices are proven to have a lower threshold voltage roll-off, reduced DIBL, better subthreshold slope characteristics, and a better gate capacitance in comparison with the C-FinFET. Moreover, the simulation result with three-dimensional and two-carrier device simulator demonstrates an improved output characteristic of the proposed structure due to reduction of self-heating effect. Due to the rounded shape of the lower fin region and decreasing corner effects there, the heat can flow easily, and the device temperature will decrease. Also the gate control over the channel increases due to the narrow upper part of the fin. The paper, thus, attempts to show the advantages of higher performance AC-FinFET device over the conventional one, and its effect on the operation of nanoscale devices.     

氧对IZO低压无结薄膜晶体管稳定性的影响

本文在室温下制备了无结结构的低压氧化铟锌薄膜晶体管, 并研究了氧分压对其稳定性的影响. 氧化铟锌无结薄膜晶体管具有迁移率高、结构新颖等优点, 然而氧化物沟道层易受氧、水分子等影响, 造成稳定性下降. 在室温下, 本文通过改变高纯氧流量制备氧化铟锌透明导电薄膜作为沟道层、源漏电极, 分析了氧压对于氧化物无结薄膜晶体管稳定性的影响. 为使晶体管在低电压(<2 V)下工作, 达到低压驱动效果, 本文采用具有双电层效应和栅电容大的二氧化硅纳米颗粒膜作为栅介质; 通过电学性能测试, 制备的晶体管工作电压仅为1 V、 开关电流比大于10⁶、亚阈值斜率小于100 mV/decade以及场效 应迁移率大于20 cm²/V·s. 实验研究表明, 通氧制备的氧化铟锌薄膜的电阻率会上升, 导致晶体管的阈值电压向正向漂移, 最终使晶体管的工作模式由耗尽型转变为增强型. 关键词： 薄膜晶体管 无结 氧化铟锌 氧分子     

超短沟道绝缘层上硅平面场效应晶体管中热载流子注入应力导致的退化对沟道长度的依赖性

随着场效应晶体管(MOSFET)器件尺寸的进一步缩小和器件新结构的引入, 学术界和工业界对器件中热载流子注入(hot carrier injections, HCI)所引起的可靠性问题日益关注. 本文研究了超短沟道长度(L=30–150 nm)绝缘层上硅(silicon on insulator, SOI)场效应晶体管在HCI应力下的电学性能退化机理. 研究结果表明, 在超短沟道情况下, HCI 应力导致的退化随着沟道长度变小而减轻. 通过研究不同栅长器件的恢复特性可以看出, 该现象是由于随着沟道长度的减小, HCI应力下偏压温度不稳定性效应所占比例变大而导致的. 此外, 本文关于SOI器件中HCI应力导致的退化和器件栅长关系的结果与最近报道的鳍式场效晶体管(FinFET)中的结果相反. 因此, 在超短沟道情况下, SOI平面MOSFET器件有可能具有比FinFET器件更好的HCI可靠性.     

高k介质异质栅全耗尽SOI MOSFET二维解析模型

为了研究高介电常数(高k)栅介质材料异质栅中绝缘衬底上的硅和金属-氧化物-硅场效应晶体管的短沟道效应,为新结构器件建立了全耗尽条件下表面势和阈值电压的二维解析模型.模型中考虑了各种主要因素的影响,包括不同介电常数材料的影响,栅金属长度及其功函数变化的影响,不同漏电压对短沟道效应的影响.结果表明,沟道表面势中引入了阶梯分布,因此源端电场较强;同时漏电压引起的电势变化可以被屏蔽,抑制短沟道效应.栅介电常数增大,也可以较好的抑制短沟道效应.解析模型与数值模拟软件ISE所得结果高度吻合. 关键词： 异质栅 绝缘衬底上的硅 阈值电压 解析模型     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

A high-side thin-layer silicon-on-insulator (SOI) pLDMOS is proposed, adopting field implant (FI) and multiple field plate (MFP) technologies. The breakdown mechanisms of back gate (BG) turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μ m thick thin-layer SOI.     

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.