Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism

For the first time, we have presented a novel nanoscale fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI-MOSFET) with modified current mechanism for leakage current reduction. The key idea in this work is to suppress the leakage current by injected carriers decrement into the channel from the source in weak inversion regime while we have created a built-in electric field in the channel for improving the on current of device. Therefore, we have introduced a trapezoidal doping that distributed vertically in the channel and called the proposed structure as vertical trapezoid doping fully depleted silicon-on-insulator MOSFET (VTD-SOI). Using two-dimensional two-carrier simulation we demonstrate that the VTD-SOI decreases the leakage current in comparison with conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI). Also, our results show short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement in the proposed structure. Therefore, the VTD-SOI structure shows excellent performance for scaled transistors in comparison with the C-SOI and can be a good candidate for CMOS low power circuits.     

单Halo全耗尽应变Si 绝缘硅金属氧化物半导体场效应管的阈值电压解析模型

为了改善金属氧化物半导体场效应管(MOSFET) 的短沟道效应(SCE)、 漏致势垒降低(DIBL) 效应, 提高电流的驱动能力, 提出了单Halo 全耗尽应变硅绝缘体 (SOI) MOSFET 结构, 该结构结合了应变Si, 峰值掺杂Halo结构, SOI 三者的优点. 通过求解二维泊松方程, 建立了全耗尽器件表面势和阈值电压的解析模型. 模型中分析了弛豫层中的Ge组分对表面势、表面场强和阈值电压的影响, 不同漏电压对表面势的影响, Halo 掺杂对阈值电压和DIBL的影响.结果表明, 该新结构能够抑制SCE和DIBL效应, 提高载流子的输运效率. 关键词： 应变Si 阈值电压 短沟道效应 漏致势垒降低     

Model and analysis of drain induced barrier lowering effect for 4H--SiC metal semiconductor field effect transistor

Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL (drain induced barrier lowering) effect for short channel 4H--SiC metal semiconductor field effect transistors (MESFETs). An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H--SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a (channel length/channel depth) ratio, drain applied voltage V_DS and channel doping concentration N_D, thus providing a good basis for the design and modelling of short channel 4H--SiC MESFETs device.     

Novel carbon nanotube field effect transistor with graded double halo channel

A novel carbon nanotube field effect transistor with symmetric graded double halo channel (GDH–CNTFET) is presented for suppressing band to band tunneling and improving the device performance. GDH structure includes two symmetric graded haloes which are broadened throughout the channel. The doping concentration of GDH channel is at maximum level at drain/source side and is reduced gradually toward zero at the middle of channel. The doping distribution at source side of channel reduces the drain induced barrier lowering (DIBL) and the drain side suppresses the band to band tunneling effect. In addition, broadening the doping throughout the channel increases the recombination of electrons and holes and acts as an additional factor for improving the band to band tunneling. Simulation results show that applying this structure on CNTFET enhances the device performance. In comparison with double halo structure with equal saturation current, the proposed GDH structure shows better characteristics and short channel parameters. Furthermore, the delay and power delay product (PDP) analysis versus on/off current ratio shows the efficiency of the proposed GDH structure.     

A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs

In this paper, a new nanoscale graded channel gate stack (GCGS) double-gate (DG) MOSFET structure and its 2-D analytical model have been proposed, investigated and expected to suppress the short-channel-effects (SCEs) and improve the subthreshold performances for nanoelectronics applications. The model predicts a shift, increasing potential barrier, in the surface potential profile along the channel, which ensures a reduced threshold voltage roll-off and DIBL effects. In the proposed structure, the subthreshold current and subthreshold swing characteristics are greatly improved in comparison with the conventional DG MOSFETs. The developed approaches are verified and validated by the good agreement found with the numerical simulation. (GCGS) DG MOSFET can alleviate the critical problem and further improve the immunity of SCEs of CMOS-based devices in the nanoscale regime.     

Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor(quasi-EDHEMT) with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering(DIBL)was presented. Due to the metal organic chemical vapor deposition(MOCVD) grown 9-nm undoped AlGaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas(2DEG) was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1-μm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm.The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of-6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

Corner effects in double-gate/gate-all-around MOSFETs

Two kinds of corner effects existing in double-gate (DG) and gate-all-around (GAA) MOSFETs have been investigated by three-dimensional (3D) and two-dimensional (2D) simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL (drain induced barrier lowering) effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.     

A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique.     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytical model,we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET,which characterize the DIBL effect.The results show that they are significantly dependent on the drain bias,gate length as well as the thickness and doping concentration of the two channel layers.Based on this analytical model,the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

Quantum transport andI–Vcharacteristics of quantum size field effect transistor

Quantum electron transport is expected to occur in nanometer-size field effect transistors. We show that the amplitude of the transmitted wave equals 1 only when the electric field in the conducting channel is zero. By reducing the dimension of the quantum transport from bulk to a two-dimensional electron gas system, and further to a one-dimensional quantum wire, the current-bias relation is not affected while the gate control over the drain current weakens. Starting from the Poisson and Schrödinger equations, we have studied numerically the quantum wave transport through the conduction channel where scattering processes are neglected, theI–Vcharacteristic of a typical heterojunction high electron mobility transistor shows a linear relationship between drain current and voltage at low drain bias, but the drain current decreases with increasing drain voltage at a high bias.     

Electrical behavior of amorphous indium–gallium–zinc oxide thin film transistors by embedding Au nanoparticles in the channel layer

We reported the effects on the electrical behavior of amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) after introducing various positions and sizes of Au nanoparticles (NPs) in the channel layer. These TFTs showed an off-current increase and threshold voltage (V_th) shift compared to conventional a-IGZO TFTs. The effects of Au NPs are explained to form the carrier conduction path which causes the current leakage in the channel layer, and act as either electron injection sites or trap sites. Therefore, this study demonstrates that the optimized control of size and position of Au NPs in the channel layer is crucial for its application in the electrical stability improvement and V_th control of a-IGZO TFTs.     

漏致势垒降低效应对短沟道应变硅金属氧化物半导体场效应管阈值电压的影响

结合应变硅金属氧化物半导体场效应管(MOSFET)结构,通过求解二维泊松方程,得到了应变Si沟道的电势分布,并据此建立了短沟道应变硅NMOSFET的阈值电压模型.依据计算结果,详细分析了弛豫Si_1－βGe_β中锗组分β、沟道长度、漏电压、衬底掺杂浓度以及沟道掺杂浓度对阈值电压的影响,从而得到漏致势垒降低效应对小尺寸应变硅器件阈值电压的影响,对应变硅器件以及电路的设计具有重要的参考价值. 关键词： 应变硅金属氧化物半导体场效应管 漏致势垒降低 二维泊松方程 阈值电压模型     

Hot carrier degradation mechanism interpretation by lateral distribution of interface and bulk trap density

We investigated the drain avalanche hot carrier effect (DAHC) of p-type metal-oxide-semiconductor field effect transistor of 0.14 μm channel length (PMOSFET) with SiON gate dielectric. Using three different stress conditions of substrate maximum current, the changes to threshold voltage, maximum transconductance, saturation current and channel leakage current was monitored. Concurrently, the lateral distribution of interface trap density (N_it) and bulk trapped charge density (N_ot) with stress time has been extracted along the 70 nm half channels from gate edge to drain junction, which is the first endeavor in describing charge traps along sub 100 nm short channels. The degradation of the PMOSFET was described by combining electrical property with N_it and N_ot profiles. Hot electron punch through (HEIP) effect was evidenced by negative Not distribution near the drain junction while more severe hot carrier degradation was successfully demonstrated by the empirical power law dependence of the electrical parameters N_it and N_ot. We have studied the evolution of degradation behavior along highly scaled tens of nanometer channel, and N_it and N_ot profile offers systematic study and interpretation of degradation mechanism of hot carrier effect in MOSFET devices.     

Comprehensive study of a 4H–SiC MES–MOSFET

In this paper, we studied the enhancement of the breakdown voltage in the 4H–SiC MESFET–MOSFET (MES–MOSFET) structure which we have proposed in our previous work. We compared this structure with Conventional Bulk-MOSFET (CB-MOSFET) and Field plated Conventional Bulk-MOSFET (FCB-MOSFET) structures. The 4H–SiC MES–MOSFET structure consists of two additional schottky buried gates which behave like a Metal on Semiconductor (MES) at the interface of the active region and substrate. The motivation for this structure was to enhance the breakdown voltage by introducing a new technique of utilizing the reduced surface field (RESURF) concept. In our comparison and investigation we used a two-dimensional device simulator. Our simulation results show that the breakdown voltage of the proposed structure is 3.7 and 2.9 times larger than CB-MOSFET and FCB-MOSFET structures, respectively. We also showed that the threshold voltage and the slope of drain current (I_D) as a function of drain–source voltage (V_DS) for all the structures is the same.     

Exploring the warped bulk

In this study, a gallium nitride (GaN) high electron mobility transistor (HEMT) with recessed insulator and barrier is reported. In the proposed structure, insulator is recessed into the barrier at the drain side and barrier is recessed into the buffer layer at the source side. We study important device characteristics such as electric field, breakdown voltage, drain current, maximum output power density, gate-drain capacitance, short channel effects and DC transconductance using two-dimensional and two-carrier device simulator. Recessed insulator in the drain side of the proposed structure reduces maximum electric field in the channel and therefore increases the breakdown voltage and maximum output power density compared to the conventional counterpart. Also, gate-drain capacitance value in the proposed structure is less than that of the conventional structure. Overall, the proposed structure reduces short channel effects. Because of the recessed regions at both the source and the drain sides, the average barrier thickness of the proposed structure is not changed. Thus, the drain current of the proposed structure is almost equivalent to that of the conventional transistor. In this work, length (L _r) and thickness (T _r) of the recessed region of the barrier at the source side are the same as those of the insulator at the drain side.     

基于非平衡Green函数理论的峰值掺杂-低掺杂漏结构碳纳米管场效应晶体管输运研究

为改善碳纳米管场效应晶体管的性能,将一种峰值掺杂-低掺杂漏(HALO-LDD)掺杂结构引入碳纳米管沟道.在量子力学非平衡Green函数理论框架内,通过自洽求解Poisson方程和Schrödinger方程,构建了适用于非均匀掺杂的碳纳米管场效应管的输运模型,该模型可实现场效应晶体管的输运性质与碳纳米管手性指数的对接. 利用该模型研究了单HALO双LDD 掺杂结构对碳纳米管场效应晶体管输运特性的影响.对比分析表明,这种非均匀掺杂结构的场效应管同本征碳纳米管沟道场效应晶体管相比,具有更低的泄漏电流、更大的电流开关比、更小的亚阈区栅电压摆幅,表明其具有更好的栅控能力; 具有更小的漏源电导,更适合应用于模拟集成电路中;具有更小的阈值电压漂移,表明更能抑制短沟道效应. 同本征沟道碳纳米管场效应晶体管相比,这种非均匀掺杂碳纳米管场效应晶体管在沟道区靠近源端位置,电场强度增大, 有利于增大电子的传输速率;在沟道区靠近漏端位置,电场强度减小,更有利于抑制热电子效应.     

60Co γ射线辐射对AlGaN/GaN HEMT器件的影响

采用⁶⁰Co γ射线辐射源对非钝化保护的AlGaN/GaN高电子迁移率晶体管(HEMT)器件进行了1 Mrad(Si)的总剂量辐射,实验发现辐射累积剂量越大,器件尺寸越小,器件饱和漏电流和跨导下降越明显,同时辐射后器件栅泄漏电流明显增大,而阈值电压变化很小. 对辐射前后器件的沟道串联电阻和阈值电压变化的分析表明,辐射感生表面态负电荷的产生是造成AlGaN/GaN HEMT器件电特性退化的主要原因之一. 关键词： AlGaN/GaN HEMT器件 γ射线辐射 表面态     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Influence of tetrabutylammonium hexafluorophosphate (TBAPF6) doping level on the performance of organic light emitting diodes based on PVK:PBD blend films

The effect of doping level of tetrabutylammonium hexafluorophosphate (TBAPF₆) on the performance of single-layer organic light emitting diodes (OLEDs) with ITO/PVK:PBD:TBAPF₆/Al structure were investigated where indium tin oxide (ITO) was used as anode, poly(9-vinylcarbazole) (PVK) as hole-transporting polymeric host, 2-(4-biphenylyl)-5-phenyl-1,3,4-oxadiazole (PBD) as electron-transporting molecule and aluminium (Al) as cathode. It was found that the doped devices underwent a unique transition at the first voltage scan as indicated by drastically increasing of current at certain applied voltage. After the transition, the threshold voltage for current injection as well as the turn-on voltage decreased significantly as compared to the undoped device. The current injection threshold voltage and turn-on voltage decreased with the increase of TBAPF₆ doping level. More importantly, a relatively low current injection threshold voltage of 3 V has been achieved by doping a significant amount of TBAPF₆ (weight ratio greater than five) in the single-layer OLED based on PVK:PBD blend films with high work function Al metal as cathode. The significant improvement was attributed to the reduction of both electron and hole injection energy barriers caused by accumulation of ionic species at the interface.