Design and fabrication of 10-kV silicon–carbide p-channel IGBTs with hexagonal cells and step space modulated junction termination extension

10-kV 4 H–SiC p-channel insulated gate bipolar transistors(IGBTs) are designed, fabricated, and characterized in this paper. The IGBTs have an active area of 2.25 mm~2 with a die size of 3 mm× 3 mm. A step space modulated junction termination extension(SSM-JTE) structure is introduced and fabricated to improve the blocking performance of the IGBTs.The SiC p-channel IGBTs with SSM-JTE termination exhibit a leakage current of only 50 nA at-10 kV. To improve the on-state characteristics of SiC IGBTs, the hexagonal cell(H-cell) structure is designed and compared with the conventional interdigital cell(I-cell) structure. At an on-state current of 50 A/cm~2, the voltage drops of I-cell IGBT and H-cell IGBT are10.1 V and 8.3 V respectively. Meanwhile, on the assumption that the package power density is 300 W/cm~2, the maximum permissible current densities of the I-cell IGBT and H-cell IGBT are determined to be 34.2 A/cm~2 and 38.9 A/cm~2 with forward voltage drops of 8.8 V and 7.8 V, respectively. The differential specific on-resistance of I-cell structure and H-cell structure IGBT are 72.36 m?·cm~2 and 56.92 m?·cm~2, respectively. These results demonstrate that H-cell structure silicon carbide IGBT with SSM-JTE is a promising candidate for high power applications.     

Temperature dependence on the electrical and physical performance of InAs/AlSb heterojunction and high electron mobility transistors

In this report, the effect of temperature on the In As/Al Sb heterojunction and high-electron-mobility transistors(HEMTs) with a gate length of 2 μm are discussed comprehensively. The results indicate that device performance is greatly improved at cryogenic temperatures. It is also observed that the device performance at 90 K is significantly improved with 27% lower gate leakage current, 12% higher maximum drain current, and 22.5% higher peak transconductance compared to 300 K. The temperature dependence of mobility and the two-dimensional electron gas concentration in the In As/Al Sb heterojunction for the temperature range 90 K-300 K is also investigated. The electron mobility at 90 K(42560 cm2/V·s)is 2.5 times higher than its value at 300 K(16911 cm~2/V·s) because of the weaker lattice vibration and the impurity ionization at cryogenic temperatures, which corresponds to a reduced scattering rate and higher mobility. We also noted that the two-dimensional electron gas concentration decreases slightly from 1.99 × 10~(12) cm~(-2) at 300 K to 1.7 × 10~(12) cm~(-2) at 90 K with a decrease in temperature due to the lower ionization at cryogenic temperature and the nearly constant ?Ec.     

Improvement in electrical properties of high-κ film on Ge substrate by an improved stress relieved pre-oxide method

High-κ /Ge gate stack has recently attracted a great deal of attention as a potential candidate to replace planar silicon transistors for sub-22 generation. However, the desorption and volatilization of GeO hamper the development of Ge-based devices. To cope with this challenge, various techniques have been proposed to improve the high-κ /Ge interface. However,these techniques have not been developed perfectly yet to control the interface. Therefore, in this paper, we propose an improved stress relieved pre-oxide(SRPO) method to improve the thermodynamic stability of the high-κ /Ge interface. The x-ray photoelectron spectroscopy(XPS) and atomic force microscopy(AFM) results indicate that the GeO volatilization of the high-κ /Ge gate stack is efficiently suppressed after 500℃ annealing, and the electrical characteristics are greatly improved.     

Quantum transport characteristics in single and multiple N-channel junctionless nanowire transistors at low temperatures

Single and multiple n-channel junctionless nanowire transistors(JNTs) are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures(10 K–100 K) and variable drain bias voltages(10 mV–90 mV). Transfer characteristics exhibit current oscillation peaks below flat-band voltage(VFB) at temperatures up to 75 K,which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional(1D) channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.     

AlGaN/GaN HEMTs on 4-Inch Silicon Substrates in the Presence of 2.7-μm -Thick Epilayers with the Maximum Off-State Breakdown Voltage of 500 V

We report on the high breakdown performance of AlGaN/GaN high electron mobility transistors （HEMTs） grown on 4-inch silicon substrates. The HEMT structure including three Al-content step-graded AlGaN transition layers has a total thickness of 2.7 μm. The HEMT with a gate width WG of 300 μm acquires a maximum off-state breakdown voltage （BV） of 550 V and a maximum drain current of 527 mA/mm at a gate voltage of 2 V. It is found that BV is improved with the increase of gate-drain distance LGD until it exceeds 8 μm and then BV is tended to saturation. While the maximum drain current drops continuously with the increase of LGD. The HEMT with a WG of 3 mm and a LGD of 8 μm obtains an off-state BV of 500 V. Its maximum leakage current is just 13 μA when the drain voltage is below 400 V. The device exhibits a maximum output current of 1 A with a maximum transconductance of 242 mS.     

High Performance P-Channel Schottky Barrier MOSFETs with Self-Aligned PtSi Source／Drain on Thin Film SOI Substrate

P-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with PtSi Schottky barrier source/drain, high-k gate dielectric and metal gate electrode were fabricated on a thin p-type silicon-on-insulator (SOl) substrate using a simplified low temperature process. The device works on a fully-depleted accumulation-mode and has an excellent electrical performance. It reaches Ion/Ioff ratio of about 10^7, subthreshold swing of 65 m V/decade and saturation drain current of Ids = 8.8 μA/μm at |Vg - Vth| = |Vd| = 1V for devices with the channel length 4.0μm and the equivalent oxide thickness 2.Onto. Compared to the corresponding bulk-Si counterparts, SOI p-SBMOSFETs have smaller off-state current due to reduction of the PtSi/Si contact area.     

Improved Performance of Organic Thin Film Transistor with an Inorganic Oxide/Polymer Double-Layer Insulator

We employ the Ta2Os/PVP （poly-4-vinylphenol） double-layer gate insulator to improve the performance of pentacene thin-film transistors. It is found that the double-layer insulator has low leakage current, smooth surface and considerably high capacitance. Compared to Ta205 insulator layers, the device with the Ta2Os/PVP doublelayer insulator exhibits an enhancement of the field-effect mobility from 0.21 to 0.54 cm2/Vs, and the decreasing threshold voltage from 4.38 V to -2.5 V. The results suggest that the Ta2Os/PVP double-layer insulator is a potential gate insulator for fabricating OTFTs with good electrical performance.     

Heterogeneous integration of InP HEMTs on quartz wafer using BCB bonding technology

Heterogeneous integrated InP high electron mobility transistors(HEMTs)on quartz wafers are fabricated successfully by using a reverse-grown InP epitaxial structure and benzocyclobutene(BCB)bonding technology.The channel of the new device is In_0.7Ga_0.3As,and the gate length is 100 nm.A maximum extrinsic transconductance gm,max of 855.5 mS/mm and a maximum drain current of 536.5 mA/mm are obtained.The current gain cutoff frequency is as high as 262 GHz and the maximum oscillation frequency reaches 288 GHz.In addition,a small signal equivalent circuit model of heterogeneous integration of InP HEMTs on quartz wafer is built to characterize device performance.     

Performance Improvement of Organic Thin Film Transistors Based on Gate Insulator Polymethyl-Methacrylate-co-Glyciclyl-Methacrylate

Organic thin transistors （OTFTs） on indium tin oxide glass substrates are prepared with polymethyl-methacrylate-co-glyciclyl-methacrylate （PMMA-GMA） as the gate insulator layer and copper phthalocyanine as the organic semiconductor layer. By controlling the thickness, the average roughness of surface is reduced and the OTFT performance is improved with leak current decreasing to 10^-11 A and on/off ratio of 10^4. Under the condition of drain-source voltage -20 V, a threshold voltage of -3.5 V is obtained. The experimental results show that PMMA-GMA is a promising insulator material with a dielectric constant in a range of 3.9-5.0.     

Analysis of non-uniform hetero-gate-dielectric dual-material control gate TFET for suppressing ambipolar nature and improving radio-frequency performance

A tunnel field-effect transistor(TFET) is proposed by combining various advantages together, such as non-uniform gate–oxide layer, hetero-gate-dielectric(HGD), and dual-material control-gate(DMCG) technology. The effects of the length of non-uniform gate–oxide layer and dual-material control-gate on the on-state, off-state, and ambipolar currents are investigated. In addition, radio-frequency performance is studied in terms of gain bandwidth product, cut-off frequency,transit time, and transconductance frequency product. Moreover, the length of non-uniform gate–oxide layer and dualmaterial control-gate are optimized to improve the on-off current ratio and radio-frequency performances as well as the suppression of ambipolar current. All results demonstrate that the proposed device not only suppresses ambipolar current but also improves radio-frequency performance compared with the conventional DMCG TFET, which makes the proposed device a better application prospect in the advanced integrated circuits.     

Characteristics Analysis of Vertical Double Gate Strained Channel Heterostructure Metal-Oxide-Semiconductor-Field-Effect-Transistor

Since device feature size shrinks continuously, there appears various short-channel effects on the fabrication and performance of devices and integrated circuits. We present a vertical double gate （VDG） strained channel heterostrueture metal-oxide-semiconduetor-field-effect-transistor （MOSFET）. The electrical characteristics of the device with the effective gate length scaled down to 60nm are simulated. The results show that the drive current and transconductance are improved by 57.92% and 54.53% respectively, and grid swing is decreased by 36.83% over their unstrained counterparts. VDG MOSFETs exhibit a stronger capability to restrict short-channel-effects over traditional MOSFETs.     

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors(NMOSFETs)is presented.In the process,a HfSiON gate dielectric with an equivalent oxide thickness of 10 A was prepared by a simple physical vapor deposition method.Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate.After the source/drain formation,the poly-Si dummy gate was removed by tetramethylammonium hydroxide(TMAH)wet-etching and replaced by a TaN metal gate.Because the metal gate was formed after the ion-implant doping activation process,the effects of the high temperature process on the metal gate were avoided.The fabricated device exhibits good electrical characteristics,including good driving ability and excellent sub-threshold characteristics.The device’s gate length is 73 nm,the driving current is 117μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μm.The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage(~0.24 V)for high performance NMOSFETs.The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.     

Numerical Study on a Lateral Double-Gate Tunnelling Field Effect Transistor

A novel lateral double-gate tunnelling field effect transistor （DG-TFET） is studied and its performance is presented by a two-dimensional device simulation with code ISE. The result demonstrates that this new tunnelling transistor allows for the steeper sub-threshold swing below 60mV/dec, the super low supply voltage （operable at VDD 〈 0.3 V） and the rail-to-rail logic （significant on-state current at the drain-source voltage VDS = 50mV） for the aggressive technology assumptions of the availability of high-k/metal stack with equivalent gate oxide thickness EOT =0.24 nm and the work function difference 4.5 eV of materials.     

Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor

The effects of gate length L_G on breakdown voltage VBRare investigated in AlGaN/GaN high-electron-mobility transistors(HEMTs) with L_G= 1 μm~20 μm. With the increase of L_G, VBRis first increased, and then saturated at LG= 3 μm. For the HEMT with L_G= 1 μm, breakdown voltage VBRis 117 V, and it can be enhanced to 148 V for the HEMT with L-_G= 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage.A similar suppression of the impact ionization exists in the HEMTs with LG 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG= 3 μm~20 μm, and their breakdown voltages are in a range of 140 V–156 V.     

A study of GaN MOSFETs with atomic-layer-deposited A1203 as the gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect transistors （MOSFETs） with atomic-layerdeposited Al₂O₃ gate dielectrics are fabricated.The device,with atomic-layer-deposited Al₂O₃ as the gate dielectric,presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm,which are better than those reported previously with Al₂O₃ as the gate dielectric.Furthermore,the device shows negligible current collapse in a wide range of bias voltages,owing to the effective passivation of the GaN surface by the Al₂O₃ film.The gate drain breakdown voltage is found to be about 59.5 V,and in addition the channel mobility of the n-GaN layer is about 380 cm2 /Vs,which is consistent with the Hall result,and it is not degraded by atomic-layer-deposition Al₂O₃ growth and device fabrication.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Enhanced mobility of MoS2 field-effect transistors by combining defect passivation with dielectric-screening effect

A facile method of combining the defect engineering with the dielectric-screening effect is proposed to improve the electrical performance of MoS₂ transistors. It is found that the carrier mobility of the transistor after the sulfur treatment on the MoS₂ channel is greatly enhanced due to the reduction of the sulfur vacancies during vulcanization of MoS₂.Furthermore, as compared to those transistors with HfO2 and SiO2 as the gate dielectric, the Al2O3-gate dielectric MoS₂ FET shows a better electrical performance after the sulfur treatment, with a lowered subthreshold swing of 179.4 m V/dec,an increased on/off ratio of 2.11 × 10⁶, and an enhanced carrier mobility of 64.74 cm²/V·s(about twice increase relative to the non-treated MoS₂ transistor with SiO2 as the gate dielectric). These are mainly attributed to the fact that a suitable k-value gate dielectric can produce a dominant dielectric-screening effect overwhelming the phonon scattering, increasing the carrier mobility, while a larger k-value gate dielectric will enhance the phonon scattering to counteract the dielectricscreening effect, reducing the carrier mobility.     

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor(CMOS) technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size(12 nm) and areal density(1.8×10~(11)/cm~2) of Si-NCs.The program/erase(P/E) speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.     

Performance of La₂O₃/InAlN/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La2O3/InAlN/GaN metal-oxide-semiconductor high electron mobility transistors(MOSHEMTs) and InAlN/GaN high electron mobility transistors(HEMTs).The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device,while the gate leakage current in the reverse direction could be reduced by four orders of magnitude.Compared with the HEMT device of a similar geometry,MOSHEMT presents a large gate voltage swing and negligible current collapse.     

Influence of Post-Annealing on Electrical Characteristics of Thin-Film Transistors with Atomic-Layer-Deposited ZnO-Channel/Al_2O_3-Dielectric

High-performance thin-film transistors(TFTs) with a low thermal budget are highly desired for flexible electronic applications.In this work,the TFTs with atomic layer deposited ZnO-channel/Al_2O_3-dielectric are fabricated under the maximum process temperature of 200℃.First,we investigate the effect of post-annealing environment such as N_2,H_2-N_2(4%) and O_2 on the device performance,revealing that O_2 annealing can greatly enhance the device performance.Further,we compare the influences of annealing temperature and time on the device performance.It is found that long annealing at 200℃ is equivalent to and even outperforms short annealing at 300℃.Excellent electrical characteristics of the TFTs are demonstrated after O_2 annealing at 200℃ for 35 min,including a low off-current of 2.3 × 10~(-13) A,a small sub-threshold swing of 245mV/dec,a large on/off current ratio of 7.6×10~8,and a high electron effective mobility of 22.1cm~2/V·s.Under negative gate bias stress at — 10 V,the above devices show better electrical stabilities than those post-annealed at 300℃.Thus the fabricated high-performance ZnO TFT with a low thermal budget is very promising for flexible electronic applications.