红外焦平面读出电路片上驱动电路设计

线列红外焦平面读出电路在正常工作时需要提供多路数字脉冲和多路直流偏置电压。本文基于0.5 μm CMOS工艺设计了一款驱动电路芯片,为电容负反馈放大型（CTIA）读出电路（ROIC）提供驱动信号。电路芯片采用带隙基准电路产生低噪声低温漂的直流偏置电压,采用数字逻辑电路生成CLK1,CLK2,RESET等八路数字脉冲。仿真及测试结果表明：驱动电路芯片输出的数字脉冲及偏置电压符合设计值,可驱动CTIA型线列红外焦平面读出电路稳定工作。     

新型无TEC的非制冷IRFPA读出电路研究

为了降低非制冷红外焦平面阵列的功耗,研究了去除热电制冷器（TEC）等温度稳定装置的读出电路。通过对微测辐射热计的电阻温度特性的分析,设计了一种新型无需温度稳定装置的读出电路,该电路的Flash存储器存储不同温度下的校正系数,温度传感器实时检测探测器的环境温度,从Flash中取出相应的温度校正系数送入数模转换器(DAC),通过DAC的电压输出来控制探测器偏流以进行环境温度补偿。HSPICE模拟结果表明,电路输出与探测器工作的环境温度无关,系统的总功耗下降了80%,同时电路噪声保持在一个较低的水平。     

一种用于非制冷红外焦平面阵列的低噪声高均匀性读出电路

提出了一种高均匀性低噪声的读出电路,该电路通过抑制非制冷红外焦平面阵列固定模式噪声,从而可实现高质量的红外图像.该电路前端采用了行共享的增益可控NMOS管抑制像元固定模式噪声,同时采用了新型的相关双采样电路抑制列固定模式噪声.在仿真基础上,采用了AMS 0.35μm CMOS工艺完成了16×16像元芯片的制备.对芯片的大量测试结果表明提出的读出电路可以有效地降低非制冷红外焦平面阵列的固定模式噪声,同时具有高均匀性的特点,适用于高性能非制冷红外探测器.     

边积分边读出低噪声红外焦平面读出电路研究

设计了一款低噪声InGaAs焦平面读出电路.提出一种新型相关双采样电路结构,可在边积分边读出模式下有效抑制积分电容(0.15 pF)的KTC噪声.电路经0.5 μn5 V Nwell CMOS工艺流片,测试结果符合设计目标,在高帧频边积分边读出模式下工作状态良好,电路噪声约1.7×10-4V,动态范围大于80 dB.     

应用于碲锌镉探测器逐次逼近模数转换器基准电压的研究

An on-chip reference voltage has been designed in capacitor-resister hybrid SAR ADC for CZT detector with the TSMC 0.35 μ m 2P4M CMOS process. The voltage reference has a dynamic load since using variable capacitors and resistances, which need a large driving ability to deal with the current related to the time and sampling rate. Most of the previous articles about the reference for ADC present only the bandgap part for a low temperature coefficient and high PSRR. However, it is not enough and overall, it needs to consider the output driving ability. The proposed voltage reference is realized by the band-gap reference, voltage generator and output buffer. Apart from a low temperature coefficient and high PSRR, it has the features of a large driving ability and low power consumption. What is more, for CZT detectors application in space, a radiation-hardened design has been considered. The measurement results show that the output reference voltage of the buffer is 4.096 V. When the temperature varied from 0 to 80℃, the temperature coefficient is 12.2 ppm/℃. The PSRR was-70 dB@100 kHz. The drive current of the reference can reach up to 10 mA. The area of the voltage reference in the SAR ADC chip is only 449×614 μm². The total power consumption is only 1.092 mW.     

基于电容读出的非制冷红外探测器

介绍了一种基于标准硅工艺的电容读出式微悬臂梁非制冷红外探测器的设计、制作以及集成读出电路的设计。该探测器用于探测室温下物体的红外辐射,其响应波长为8～12 μm 。由于氮化硅和铝的热膨胀系数相差很大,用这两种材料的薄膜做成的双材料微悬臂梁在红外辐射下会发生弯曲,微悬臂梁和衬底形成一个可变电容,通过检测电容的变化来反映微悬臂梁的弯曲,从而可以探测红外辐射的情况。采用和探测器集成的CMOS读出电路对探测器信号进行读取,微悬臂梁的电容灵敏度可达2.5 fF/K,温度分辨率为0.1 K。     

红外焦平面信号读出及处理技术

读出电路是红外探测器组件的重要组成部分,其性能对组件乃至整个成像系统的性能影响重大。本文旨在说明根据不同类型的红外探测器及应用需求特点,读出电路应采取相应的信号读出处理技术,以提高组件性能。文章介绍了适用于不同探测器及应用需求的源随输入级、直接注入输入级、容性反馈放大器输入级信号读出技术,相关双采样低噪声处理技术以及像素级数字化技术。     

一种程控实现任意行选的红外焦平面读出电路

设计了一种可应用于多光谱红外光谱仪的红外焦平面读出集成电路。电路可以选择任意连续或非连续行的积分信号进行读出而无须逐行读出,从而大大增加了系统的灵活性和帧频。同时,电路采用滚动式IWR工作模式,为此根据读出单元是否有积分开关设计了两种复位积分控制模块;单元内部可采用DI,CTIA等读出结构。此电路具有明确的工程应用价值。     

一种高灵敏度数字化TDI型红外焦平面读出电路

数字化红外焦平面探测技术作为第三代红外焦平面技术成为近年来被研究的热点.本文提出了一种将像素级数字化技术与TDI技术相结合的红外焦平面读出电路,使得电路实现大动态范围的同时满足低功耗设计.文中在0.18μm CMOS工艺模型下,对电路进行设计仿真,该读出电路电荷处理能力可达到5.04 Ge-,动态范围最高达到101.5...     

A snap-shot mode cryogenic readout circuit for QWIP IR FPAs

The design and measurement of a snap-shot mode cryogenic readout circuit (ROIC) for GaAs/AlGaAs QWIP FPAs was reported. CTIA input circuits with pixel level built-in electronic injection transistors were proposed to test the chip before assembly with a detector array. Design optimization techniques for cryogenic and low power are analyzed. An experimental ROIC chip of a 128 × 128 array was fabricated in 0.35μm CMOS technology. Measure-ments showed that the ROIC could operate at 77 K with low power dissipation of 35 mW. The chip has a pixel charge capacity of 2.57 × 10~6 electrons and transimpedance of 1.4 × 10~7 Ω. Measurements showed that the transimpedance non-uniformity was less than 5% with a 10 MHz readout speed and a 3.3 V supply voltage.     

一种用于红外读出电路的低温SAR ADC

本文提出了一种用于低温红外读出系统的连续逼近模数转换器（SAR ADC）电路。为了在很宽的温度范围内保证电路的性能,ADC中采用了一种温度补偿时域比较器结构。该比较器可在从室温到77K的极端工作温度条件下,实现稳定的性能和极低的功耗。该转换器采用标准的 0.35 μm CMOS 工艺制造,在77K的温度下,其最大微分非线性（DNL）和积分非线性（INL）分别为0.64LSB和0.59LSB。在采样率为200kS/s时可实现9.3bit的有效位数。在3.3V的电源电压下其功耗为0.23mW,占用的芯片面积为0.8*0.3 mm2。     

面向QWIP焦平面阵列的快照模式低温读出电路

介绍了应用于GaAs/AlGaAs量子阱红外焦平面阵列的快照模式的低温读出电路的设计方法与测试结果。读出电路采用CTIA作为输入电路,提出在单元输入电路中引入内建电注入器件进行读出电路封装前测试。对读出电路的低温和低功耗进行了优化设计。基于该方法采用0.35um CMOS工艺设计制造了阵列尺寸为128×128的读出电路实验芯片。测试结果表明,读出电路能够在77K的温度下正常工作,功耗为35mW。该读出电路象元级的电荷容量为2.57×106电子,跨导系数为1.4×107Ω。分析表明,在3.3V电源电压下,当输出速率为10MHz时,实验芯片的非均匀性小于5%。     

应用于高速CMOS图像传感器的10比特列并行循环式ADC

This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.     

A cryogenic SAR ADC for infrared readout circuits

A cryogenic successive approximation register(SAR) analog to digital converter(ADC) is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature.In order to preserve the circuit’s performance over this wide temperature range,a temperature-compensated time-based comparator architecture is used in the ADC,which provides a steady performance with ultra low power for extreme temperature(from room temperature down to 77 K) operation.The converter implemented in a standard 0.35μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity (DNL) and 0.59 LSB maximum integral nonlinearity(INL).It achieves 9.3 bit effective number of bits(ENOB) with 200 kS/s sampling rate at 77 K,dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8×0.3 mm~2.     

带有失配修正的10-bit 250-KSPS低功耗循环ADC设计

本为提出了一种10-bit 250k采样率（KSPS）的循环模数转换器（ADC）。通过适当的选取电容开关时序,ADC的失调误差被有效的消除。改进的冗余有符号数（RSD）法则能够容忍较大的比较器失调误差与开关电容失配误差。通过采用这种结构,ADC具有了电路结构简单、占用芯片面积低以及低功耗的优点。该循环ADC采用Chartered 0.35 um 2P4M工艺制造,在250k的采样率下,其信号对噪声和失真比（SNDR）为58.5dB,有效位数（ENOB）为9.4bit。该电路在3.3V的电源电压下,功耗为0.72mW,占有芯片面积0.42×0.68 mm2。     

总剂量效应对CMOS读出电路影响及设计加固方法研究

总剂量效应会对CMOS读出电路的性能产生明显的影响,甚至使CMOS读出电路功能完全失效。本文主要分析了总剂量效应对NMOS器件阈值、漏电流和器件间漏电流的影响机理。随后,针对640×512 CMOS读出电路提出了可行的抗辐照版图设计方法。总剂量试验表明,采用环栅结构、环源结构的640×512读出电路芯片抗总剂量能力可以达到100 krad(Si)以上。     

基于自偏置电流镜的CMOS红外焦平面读出电路

针对高精度红外焦平面阵列应用设计了一种具有高注入效率、大动态范围、稳定的探测器偏压、小面积和低功耗的自偏置电流镜注入CMOS读出电路.所设计的电路结构包括一种由自偏置的宽摆幅PMOS共源共栅电流镜和NMOS电流镜构成的反馈结构读出单元电路和相关双采样电路.对所设计电路采用Chartered 0.35 μm CMOS工艺进行了流片.测试结果显示:电路线性度达到了99%,探测器两端偏压小于1mV.电路输入阻抗近似为0,单元电路面积为10μm×15μm,功耗小于0.4μW.电量存储能力3108电子.测试结果表明:电路功能和性能都达到了设计要求.     

A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction

A low power 10-bit 250-k sample per second(KSPS) cyclic analog to digital converter(ADC) is presented. The ADC’s offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence.The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator’s offset errors and switched capacitor mismatch errors.With this structure,it has the advantages of simple circuit configuration,small chip area and low power dissipation.The cyclic ADC manufactured with the Chartered 0.35μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate.It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42×0.68 mm~2.     

一种具有高填充因子吸收层和低失调低噪声读出电路的红外探测系统

使用红外探测器及读出电路,研制成功非制冷红外探测系统.探测器用二极管作为温度传感器,使其与集成电路工艺相兼容.采用了新的器件结构,使得填充因子从20%提高到80%.器件的微机械结构面积为35μm×35μm.读出电路的失调电压为3μV.探测器的输出噪声为2μV.探测器的电压响应率为7 894.7 V/W,黑体探测率D*为1.56×109cmHz1/2/W,噪声等效温差为330 mK,响应时间为27 ms.     

二极管非制冷红外探测器及其读出电路设计

针对非制冷红外技术的低成本高性能应用,提出了基于SOI的二极管红外探测器及其读出电路的集成设计方案。阐述了二极管非制冷红外探测器的基本原理和工艺实现。对探测器的电学特性进行理论推导,得出读出电路的设计指标。采用连续时间自稳零电路结构实现探测器输出信号的低噪声低失调放大,采用级联滤波器以减弱开关非理想因素的影响,并采用片内电容采样保持,使得I/O引脚数较少,从而减小版图面积。采用spectre工具进行仿真,在CSMC 0.5 m 2P3M CMOS工艺下实现。结果表明:读出电路性能良好,闭环增益为65.8 dB,等效输入噪声谱密度为450 nV/Hz,等效输入失调电压100 V以内,功耗为5 mW,能实现探测器信号的准确读出。