Reliability analysis of a fault tolerant computer system

This paper investigates a mathematical model of an information computer network system. In this model, the system has two parts—a controller and a terminal. It is also linked with a satellite by a disk antenna. Each part has two failure modes; one is transient failure and second is latent failure. After latent failure, the terminal is recoverable, but the controller is not recoverable. The system may also fail due to a common-cause failure when it is in the normal state or in a partially normal state. Failure rates are constant and recovery rates are general. Using the regenerative point technique several measures of system effectiveness are obtained.     

一类数字容错系统的可靠性分析

在大多数关键的数字系统中，容错性已经成为提高系统可靠性的本质特征，提高容错系统可靠性的技术越来越引起人们的注意。本文根据一种在数据通信中常见的容错系统建立了可靠性分析模型，并对该容错系统的可靠性进行定量分析。同时，本文还以一个双机备份通信系统为例说明这种可靠性分析方法。     

A novel fault tolerant token ring network

Token Ring Networks have gained popularity due to their simplicity and ease of maintenance. However, the functioning of the entire network is dependent on the well being of an entity called “token”. The network ceases to function if the token is lost. There are algorithms suggested for improving the fault tolerant capabilities of the network with respect to the token.This paper proposes an algorithm to achieve fault tolerance. The algorithm is implemented on a simulated token ring network.     

Reliability analysis and redundancy optimisation of a multimodular fault tolerant system

This paper presents the reliability analysis of a multimodular fault-tolerant system having N-modules in parallel. The reliability and MTSF of the system have been calculated and the expression for optimum number of modules has also been obtained with cost constraint in view.     

Reconfigurable fault tolerant networks for fast packet switching

The authors consider the design and analysis of reconfigurable networks for fast packet switching. The design constraints resulting from the use of fast packet switching that affect fault-tolerant network design are carefully studied. A reconfigurable network with high link redundancy is then proposed. An abstract replacement model that characterizes the proposed reconfigurable network is presented. Network fault tolerance problems are transformed into well known assignment problems. Two practical designs based on feasible technology are presented. An appreciable reliability improvements is achieved and full bandwidth is maintained up to a tolerable level of failures, with relatively few spare switches     

Stochastic analysis of a fault tolerant network system

This paper deals with a stochastic model related to a converter-based communication network system. In this model two converters are connected in parallel with a network system. Each converter has two failure modes—transient failure and latent failure. Transient failures occur due to minor faults in converters. Further the converter may enter into the latent failure mode if major hardware problems arise in the transient failure mode. The converter may recover automatically when it is in a transient failure mode and needs repair when it is in a latent failure mode. The system also enters preventive maintenance at random epochs when both converters are normal. System failure occurs when both the converters are in a latent failure mode. Using the regenerative point technique, various reliability measures are obtained.     

QoS aware and fault tolerant handovers in software defined LTE networks

Wireless Networks - In order to handle a huge number of mobile users connections and their requirements like higher throughput, lower delay and seamless mobility, telecom operators have started...     

Performance analysis of minimal path fault tolerant routing in NoC

Occurrence of faults in Network on Chip (NoC) is inevitable as the feature size is continuously decreasing and processing elements are increasing in numbers. Faults can be revocable if it is transient. Transient fault may occur inside router, or in the core or in communication wires. Examples of transient faults are overflow of buffers in router, clock skew, cross talk, etc.. Revocation of transient faults can be done by retransmission of faulty packets using oblivious or adaptive routing algorithms. Irrevocable faults causes non-functionality of segment and mainly occurs during fabrication process. NoC reliability increases with the efficient routing algorithms, which can handle the maximum faults without deadlock in network. As transient faults are temporary and can be easily revoked using retransmission of packet, permanent faults require efficient routing to route the packet by bypassing the nonfunctional segments. Thus, our focus is on the analysis of adaptive minimal path fault tolerant routing to handle the permanent faults. Comparative analysis between partial adaptive fault tolerance routing West-First, North-Last, Negative-First, Odd Even, and Minimal path Fault Tolerant routing (MinFT) algorithms with the nodes and links failure is performed using NoC Interconnect RoutinG and Application Modeling simulator (NIRGAM) for the 2D Mesh topology. Result suggests that MinFT ensures data transmission under worst conditions as compared to other adaptive routing algorithms.     

内进化容错模型设计及其可靠性分析

仿照自然界的碳基生物进化过程,在FPGA内部实现了可控的硅基进化。针对电子系统常见的SA故障,提出了基于演化硬件技术的内进化容错模型,通过在FPGA内部装载Microblaze CPU和构建可重配置阵列,实现了演化硬件的片内进化。利用该模型进行了故障容错实验,检验了其有效的故障容错能力,证明该容错方法能够有效提高数字电路的可靠性。     

Reliability of local area networks with bus and ring topologies

The reliability of local area networks with bus and ring topologies with a simple transfer medium are critically analysed. A double transfer medium is used to increase reliability. The efficiencies of these approaches are compared.     

A reliable quality of service aware fault tolerant gateway discovery protocol for vehicular networks

A great interest in vehicular ad‐hoc networks has been noticed by the research community. General goals of vehicular networks are to enhance safety on the road and to ensure the convenience of passengers by continuously providing them, in real time, with information and entertainment options such as routes to destinations, traffic conditions, facilities' information, and multimedia/Internet access. Indeed, time efficient systems that have high connectivity and low bandwidth usage are most needed to cope with realistic traffic mobility conditions. One foundation of such a system is the design of an efficient gateway discovery protocol that guarantees robust connectivity between vehicles, while assuring Internet access. Little work has been performed on how to concurrently integrate load balancing, quality of service (QoS), and fault tolerant mechanisms into these protocols. In this paper, we propose a reliable QoS‐aware and location aided gateway discovery protocol for vehicular networks by the name of fault tolerant location‐based gateway advertisement and discovery. One of the features of this protocol is its ability to tolerate gateway routers and/or road vehicle failure. Moreover, this protocol takes into consideration the aspects of the QoS requirements specified by the gateway requesters; furthermore, the protocol insures load balancing on the gateways as well as on the routes between gateways and gateway clients. We discuss its implementation and report on its performance in contrast with similar protocols through extensive simulation experiments using the ns‐2 simulator. Copyright © 2013 John Wiley & Sons, Ltd.     

Reliability analysis of redundant-path interconnection networks

The reliability of some redundant-path multistage interconnection networks is characterized. The classes of networks are the generalized indra networks, merged delta networks, and augmented C-networks. The reliability measures are terminal reliability and broadcast reliability. Symbolic expressions are derived for these reliability measures in terms of component reliabilities. The results are useful in comparing network designs for a given reliability requirement     

On fault tolerant matrix decomposition

We present a fault tolerant algorithm for matrix factorization in the presence of multiple hardware faults which can be used for solving the linear systemAx=b without determining the correctZU decomposition ofA. HereZ is eitherL for ordinary Gaussian decomposition with partial pivoting,X for pairwise or neighbor pivoting (motivated by the Gentleman-Kung systolic array structure), orQ for the usualQR decomposition. Our algorithm generalizes that of Luk and Park whose method allows for the correction of a single error in a single iterate of the matrixU. Using ideas from the theory of error correcting codes we prove that the algorithm of Luk and Park can in fact tolerate multiple errors in multiple iterates ofU provided these are all confined to a single column. We then generalize the algorithm to one that tolerates multiple errors in multiple iterates ofU provided they are confined to two columns. Our procedure for identifying the erroneous columns is based on the extended Euclidean algorithm and it analogous to the decoding algorithms for BCH codes. We indicate how our methods may be adapted to apply to any number of columns and finally we show how to compute a correct factorization ofA.The author gratefully acknowledeges financial support from the International Fund for Ireland. ¢Controller, HMSO, London, 1991.     

Analysis of fault tolerant computer systems

In many critical applications of digital systems, fault tolerance has been an essential architectural attribute for achieving high reliability. In recent years, the concept of the performability of such systems has drawn the attention of many researchers. In this paper we develop a general Markov model for fault tolerant computer systems. Various important performance measures, including the performability measures as well as some new performance measures, are treated in a unified manner. Furthermore, general and efficient computational procedures are developed for calculating these performance measures based on the uniformization technique of Keilson. A numerical example is given to illustrate the computational procedures developed.     

A distributed algorithm for energy efficient and fault tolerant routing in wireless sensor networks

Wireless Networks - Energy conservation and fault tolerance are the most two important challenging issues for the development of large scale wireless sensor networks (WSNs). Failure of cluster...     

Reliability analysis of interconnection networks using hierarchicalcomposition

Based on the nature of the upper- and lower-bound block diagram models of multistage interconnection networks (MINs), a series system consisting of independent subsystems is considered. To model the reliability of such a system with online repair and imperfect coverage, the usual approach is to construct and solve a large, overall Markov model. A two-level hierarchical model is instead proposed in which each subsystem is modeled as a Markov chain and the system reliability is then modeled as a series system of independent Markov components. This technique is extended to compute the instantaneous availability of the system with imperfect coverage and online repair. Extensions to allow for transient faults and phase-type repair time distributions are straightforward. It should be possible to apply this approach to other fault-tolerant MINs and to any system that can be modeled as a series system where each subsystem has a parallel-redundant structure     

Bio-inspired fault tolerant network on chip

The integration of heterogeneous processing elements (PEs) or nodes in the System on Chip (SoC) has made the communication structure very complex. The bus based system between these components is not able to handle the communication requirements and, this has led to the idea of Network on Chip (NoC). The NoC addresses the communication requirement of different nodes on SoC. The physical sizes of devices in NoC are scaled down, including routers, processing elements and interconnects, giving rise to faults, system delay, and latency issues. Fault tolerant routing algorithms are used to recover from temporary faults while redundant resources (wires, routers) are required to overcome the permanent faults. These routing algorithms, however, still suffer from congestion problems, low bandwidth, and throughput utilization as well as lacking adaptivity and robustness. In this work, novel biologically inspired techniques were proposed for NoC using combined best effort (BE) and guaranteed throughput (GT) services. Moreover, the bio-inspired algorithms are compared and analyzed with each other using BE, GT and combined BE-GT services. The bio-inspired mechanisms of “synaptogenesis” and “sprouting” have been adopted in the proposed NoC algorithms and architecture. These techniques were implemented using the BE and GT services. With the help of these two bio-inspired techniques, the NoC becomes robust, fault tolerant and is able to efficiently utilize the throughput and bandwidth. The bio-inspired algorithms improved the accepted traffic (flit/cycle/node) by 38.99% compared to different techniques in the literature. The bio-inspired algorithm also improved the bandwidth and throughput utilization by 71.04% and 72.42% respectively compared to the XY and Odd-Even fault tolerant routing algorithms. Moreover, the bio-inspired algorithm had less end-to-end latency and interflit arrival time by 196.44% and 88.10% respectively compared to the literature techniques of XY and Odd-Even.     

Clos-based fault tolerant multicast ATM switch

A Clos-based fault tolerant multicast ATM switch is proposed in which each stage has one more redundant switch module. If one switch module is faulty, the redundant module replaces the faulty module. On the other hand, even under fault-free conditions, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance