SiO2固态电解质中的质子特性对氧化物双电层薄膜晶体管性能的影响

本文采用等离子体增强化学气相沉积技术(PECVD)在室温条件下制备了具有双电层效应的二氧化硅(SiO₂) 固体电解质薄膜, 并以此SiO₂薄膜作为栅介质制备了氧化铟锌(IZO)双电层薄膜晶体管. 本文系统地研究了SiO₂固体电解质中的质子特性对双电层薄膜晶体管性能的影响, 研究结果表明, 经过纯水浸泡的SiO₂固体电解质薄膜可以诱导出较多的可迁移质子, 因此表现出较大的双电层电容. 由于SiO₂固体电解质薄膜具有质子迁移特性, 晶体管的转移特性曲线呈现出逆时针方向的洄滞现象, 并且这一洄滞效应随着栅极电压扫描速率的增加而增大. 进一步对薄膜晶体管的偏压稳定性进行测试, 发现晶体管的阈值电压的变化遵循了拉升指数函数(stretched exponential function)关系.     

基于P掺杂SiO2为栅介质的超低压侧栅薄膜晶体管

在室温下利用等离子体增强化学气相沉积法(PECVD)制备的颗粒膜P掺杂SiO₂为栅介质, 使用磁控溅射方法利用一步掩模法制备出一种新型结构的侧栅薄膜晶体管. 由于侧栅薄膜晶体管具有独特的结构, 在射频磁控溅射过程中, 仅仅利用一块镍掩模板, 无需复杂的光刻步骤, 就可同时沉积出氧化铟锡(ITO)源、漏、栅电极和沟道, 因此, 这种方法极大地简化了制备流程, 降低了工艺成本. 实验结果表明, 在P掺杂SiO₂栅介质层与沟道层界面处形成了超大的双电层电容(8 μF/cm²), 这使得这类晶体管具有超低的工作电压1 V, 小的亚阈值摆幅82 mV/dec、高的迁移率18.35 cm²/V·s和大的开关电流比1.1×10⁶. 因此, 这种P掺杂SiO₂双电层超低压薄膜晶体管将有望应用于低能耗便携式电子产品以及新型传感器领域. 关键词： 2')" href="#">P掺杂SiO₂ 侧栅薄膜晶体管 双电层(EDL) 超低压     

Fabrication and characterization of the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors

In this paper, the normally-off N-channel lateral 4H–Si C metal–oxide–semiconductor field-effect transistors(MOSFFETs) have been fabricated and characterized. A sandwich-(nitridation–oxidation–nitridation) type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H–Si C/SiO_2 were examined by the measurement of HF I–V, G–V, and C–V over a range of frequencies. The ideal C–V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H–Si C was reduced to 2 × 10~(11) e V~(-1)·cm~(-2), the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak fieldeffect mobility is about 32.5 cm~2·V~(-1)·s~(-1), and the maximum peak field-effect mobility of 38 cm~2·V~(-1)·s~(-1) was achieved in fabricated lateral 4H–Si C MOSFFETs.     

基于聚(4-乙烯基苯酚)衬底修饰层喷墨打印的小分子有机半导体薄膜制备和表征

采用旋涂法预先在SiO₂衬底表面形成一层聚（4-乙烯基苯酚）（PVP）作为表面修饰层,以喷墨打印的6,13-双（三异丙基甲硅烷基乙炔基）并五苯（TIPS并五苯）作为有源层制作有机薄膜晶体管,有效改善了有机半导体薄膜的形貌。采用真空热蒸镀工艺制备源漏电极,形成底栅顶接触结构的有机薄膜晶体管（OTFT）器件。作为对比,在未经过表面修饰的SiO₂衬底上采用相同条件打印TIPS并五苯薄膜晶体管,发现在经过PVP修饰的SiO₂衬底上打印的单点厚度更均匀,咖啡环效应被抑制或被消除;而通过多点交叠打印形成的矩形薄膜的晶粒尺寸更大,相应的OTFT器件具有更高的场效应迁移率。在有PVP修饰层的衬底上制作的OTFT,器件在饱和区的平均场效应迁移率达到了0.065 cm²·V^-1·s^-1;而直接在SiO₂衬底上制作的器件,相应的平均场效应迁移率仅为0.02 cm²·V^-1·s^-1。     

Normally-off AlGaN/GaN heterojunction field-effect transistors with in-situ AlN gate insulator

AlGaN/GaN heterojunction field-effect transistors (HFETs) with p-GaN cap layer are developed for normally-off operation, in which an in-situ grown AlN layer is utilized as the gate insulator. Compared with the SiN_x gate insulator, the AlN/p-GaN interface presents a more obvious energy band bending and a wider depletion region, which helps to positively shift the threshold voltage. In addition, the relatively large conduction band offset of AlN/p-GaN is beneficial to suppress the gate leakage current and enhance the gate breakdown voltage. Owing to the introduction of AlN layer, normally-off p-GaN capped AlGaN/GaN HFET with a threshold voltage of 4 V and a gate swing of 13 V is realized. Furthermore, the field-effect mobility is approximately 1500 cm²·V^-1·s^-1 in the 2DEG channel, implying a good device performance.     

沟道层厚度对室温制备的In2O3薄膜晶体管器件性能的影响

在室温下采用直流磁控溅射以SiO₂/Si为衬底制备了不同沟道层厚度的底栅式In₂O₃薄膜晶体管,讨论了沟道层厚度对底栅In₂O₃薄膜晶体管的电学性能的影响。实验结果表明:器件的特性与沟道层厚度有关,最优沟道层厚度的In₂O₃薄膜晶体管为增强型,其阈值电压为2.5 V,开关电流比约为10⁶,场效应迁移率为6.2 cm²·V^-1·s^-1。     

Enhanced performances of ZnO-TFT by improving surface properties of channel layer

Top-contact thin film transistors with ZnO as the channel layer and thermally grown SiO₂ as the gate dielectric were fabricated by using rf sputtering. The performances of ZnO-TFTs with different thicknesses of the active layer were investigated and the optimized condition was obtained. With the active layer thickness from 25 to 70 nm, the leakage current of devices increased from 10⁻¹⁰ to 10⁻⁸ A, and the on/off ratio decreased from 1.2×10⁷ to 2×10⁴. Atomic force microscope research indicated that with the thickness increased, the surface morphology of the active layer improved noticeably at first and then deteriorated. The 25-nm-thick ZnO TFT had the best surface morphology, and showed the best performance with a field effect mobility of 5.1 cm²/V S, on/off ratio of 1.2×10⁷ and threshold voltage of 20 V. This indicates that the surface properties of the channel layer have crucial affects on the performances of ZnO-TFTs.     

InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究

本文通过解析阵列基板栅极驱动(gate driver on array, GOA)电路中发生静电释放(electro-static discharge,ESD)的InGaZnO薄膜晶体管(InGaZnO thin-film transistor, IGZO TFT)器件发现:栅极Cu金属扩散进入了SiN_x/SiO_2栅极绝缘层;源漏极金属层成膜前就发生了ESD破坏;距离ESD破坏区域越近的IGZO TFT,电流开关比越小,直到源漏极与栅极完全短路.本文综合IGZO TFT器件工艺、GOA区与显示区金属密度比、栅极金属层与绝缘层厚度非均匀性分布等因素,采用ESD器件级分析与系统级分析相结合的方法,提出栅极Cu:SiN_x/SiO_2界面缺陷以及这三层薄膜的厚度非均匀分布是导致GOA电路中沟道宽长比大的IGZO TFT发生ESD失效的关键因素,并针对性地提出了改善方案.     

离子凝胶薄膜栅介石墨烯场效应管

在石墨烯场效应晶体管栅介结构中引入具有良好电容特性或极化特性的材料可改善晶体管性能.本文采用化学气相沉积制备的石墨烯并以PVDF-[EMIM]TF2N离子凝胶薄膜(ion-gel film)作为介质层制备底栅型石墨烯场效应管(graphene-based field effect transistor, GFET),研究其电学特性以及真空环境和温度对GFET性能的影响.结果表明离子凝胶薄膜栅介石墨烯场效应晶体管表现出良好的电学特性,室温空气环境中,与SiO_2栅介GFET相比, ion-gel膜栅介GFET开关比(J_(on)/J_(off))和跨导(g_m)分别提高至6.95和3.68×10~(–2) mS,而狄拉克电压(V_(Dirac))低至1.3 V;真空环境下ion-gel膜栅介GFET狄拉克电压最低可降至0.4 V;随着温度的升高, GFET的跨导最高可提升至6.11×10~(–2) mS.     

Time-dependent response of interface states determined by using differential isothermal transient spectroscopy

A method based on the differential analysis of the isothermal transients is proposed to study the dynamical properties of the charging and discharging of interface states, and several possibilities of using this method are shown. The results obtained in SiO₂/Si and Si₃N₄/SiO₂/Si samples are in agreement with the existence of a spatial and energy distribution of interface states within the insulator. From the experimental data, the concentration of traps within the insulator at 35 Å is estimated to be 5×10⁹ cm^-2 eV^-1, with a tunneling cross section 10^-19 cm², at E_c-E ≈ 0.2 eV.     

高迁移率聚合物薄膜晶体管

以高掺杂Si单晶片作为栅电极, 热生长SiO₂作为栅介质层, 聚三己基噻吩薄膜作为半导体活性层, Au作为源、漏电极, 并采用十八烷基三氯硅烷（OTS）对栅介质表面改性, 在空气环境下成功地制备出高性能聚合物薄膜晶体管. 结果表明, 通过采用OTS对栅介质层表面修饰大幅度地改善了聚合物薄膜晶体管的电性能, 器件的场效应迁移率高达0.02 cm²/（Vs）, 开关电流比大于10⁵. 关键词： 聚合物薄膜晶体管 聚三己基噻吩 场效应迁移率 表面修饰     

氧对IZO低压无结薄膜晶体管稳定性的影响

本文在室温下制备了无结结构的低压氧化铟锌薄膜晶体管, 并研究了氧分压对其稳定性的影响. 氧化铟锌无结薄膜晶体管具有迁移率高、结构新颖等优点, 然而氧化物沟道层易受氧、水分子等影响, 造成稳定性下降. 在室温下, 本文通过改变高纯氧流量制备氧化铟锌透明导电薄膜作为沟道层、源漏电极, 分析了氧压对于氧化物无结薄膜晶体管稳定性的影响. 为使晶体管在低电压(<2 V)下工作, 达到低压驱动效果, 本文采用具有双电层效应和栅电容大的二氧化硅纳米颗粒膜作为栅介质; 通过电学性能测试, 制备的晶体管工作电压仅为1 V、 开关电流比大于10⁶、亚阈值斜率小于100 mV/decade以及场效 应迁移率大于20 cm²/V·s. 实验研究表明, 通氧制备的氧化铟锌薄膜的电阻率会上升, 导致晶体管的阈值电压向正向漂移, 最终使晶体管的工作模式由耗尽型转变为增强型. 关键词： 薄膜晶体管 无结 氧化铟锌 氧分子     

A field-effect WSe2/Si heterojunction diode

It is significant to develop a heterogeneous integration technology to promote the application of two-dimensional (2D) materials in silicon roadmap. In this paper, we reported a field-effect WSe₂/Si heterojunction diode based on ambipolar 2D WSe₂ and silicon on insulator (SOI). Our results indicate that the device exhibits a p-n diode behavior with a rectifying ratio of ～ 300 and an ideality factor of 1.37. As a photodetector, it has optoelectronic properties with a response time of 0.13 ms, responsivity of 0.045 A/W, detectivity of 4.5×10¹⁰ Jones and external quantum efficiency (EQE) of 8.9 %. Due to the ambipolar behavior of the WSe₂, the rectifying and optoelectronic properties of the heterojunction diode can be modulated by the gate electrical field, enabling various potential applications such as logic optoelectronic devices and neuromorphic optoelectronic devices for in-sensor computing circuits. Thanks to the process based on the mature SOI technique, our field-effect heterojunction diode should have obvious advantages in device isolation and integration.     

Al_2O_3薄层修饰SiN_x绝缘层的IGZO-TFTs器件的性能研究

采用原子层沉积工艺(ALD)生长均匀致密的三氧化二铝(Al2O3)薄层对氮化硅(Si Nx)绝缘层进行修饰,研究了铟镓锌氧薄膜晶体管(IGZO-TFTs)器件的性能。当Al2O3修饰层厚度为4 nm时,绝缘层-有源层界面的最大缺陷态密度相比于未修饰器件降低了17.2%,器件性能得到显著改善。场效应迁移率由1.19 cm2/(V·s)提高到7.11 cm2/(V·s),阈值电压由39.70 V降低到25.37 V,1 h正向偏压应力下的阈值电压漂移量由2.19 V减小到1.41 V。     

Dielectrics for passivation of planar InP/InGaAs diodes

We have investigated dielectrics for passivating planar InP or InGaAs photodiodes: thermally evaporated Al₂O₃ and SiO, sputtered Si₃N₄ and SiO₂ and also SiO₂ using chemical vapour deposition. The measured bulk and field-effect properties of all dielectrics excluding sputtered SiO₂ were suitable for this application. In planar InGaAs diodes with Cd diffused or Mg implanted p⁺-region a disordered dielectric/semiconductor surface led to high reverse current densities above 1 mA/cm². In InP diodes with p⁺-diffusion and dielectrics exhibiting positive flatband voltages, e.g. Si₃N₄ and Al₂O₃, reverse current densities of 10 μA/cm² were measured probably caused by a slight inversion of the semiconductor surface. With a SiO or CVD-SiO₂ passivating layer on n-InP lowest leakage current densities (10 nA/cm²) were achieved. Very low dark-current planar photodiodes InP/InGaAsP/InGaAs have been fabricated using SiO passivation (30 nA/cm²).     

A quantum chemical study of ZrO2 atomic layer deposition growth reactions on the SiO2 surface

Zirconium oxide (ZrO₂) is one of the leading candidates to replace silicon oxide (SiO₂) as the gate dielectric for future generation metal-oxide-semiconductor (MOS) based nanoelectronic devices. Experimental studies have shown that a 1–3 monolayer SiO₂ film between the high permittivity metal oxide and the substrate silicon is needed to minimize electrical degradation. This study uses density functional theory (DFT) to investigate the initial growth reactions of ZrO₂ on hydroxylated SiO₂ by atomic layer deposition (ALD). The reactants investigated in this study are zirconium tetrachloride (ZrCl₄) and water (H₂O). Exchange reaction mechanisms for the two reaction half-cycles were investigated. For the first half-reaction, reaction of gaseous ZrCl₄ with the hydroxylated SiO₂ surface was studied. Upon adsorption, ZrCl₄ forms a stable intermediate complex with the surface SiO₂–OH^* site, followed by formation of SiO₂–O–Zr–Cl^* surface sites and HCl. For the second half-reaction, reaction of H₂O on SiO₂–O–Zr–Cl^* surface sites was investigated. The reaction pathway is analogous to that of the first half-reaction; water first forms a stable intermediate complex followed by evolution of HCl through combination of a Cl atom from the surface site and an H atom from H₂O. The results reveal that the stable intermediate complexes formed in both half-reactions can lead to a slow film growth rate unless process parameters are adjusted to lower the stability of the complex. The energetics of the two half-reactions are similar to those of ZrO₂ ALD on ZrO₂ and as well as the energetics of ZrO₂ ALD on hydroxylated silicon. The energetics of the growth reactions with two surface hydroxyl sites are also described.     

YVO_4∶Eu~(3+)@SiO_2核壳结构纳米复合材料的合成与表征

用沉淀法制备了尺寸约为8 nm的YVO4∶Eu3+纳米粒子,然后用反相微乳液法在YVO4∶Eu3+纳米粒子的表面包覆了一层Si O2壳。利用XRD、TEM、UV-Vis吸收光谱和光致发光光谱对合成的样品进行了表征。得到的复合物具有较好的核壳结构,通过改变硅酸四乙酯的用量可以改变Si O2壳的厚度。研究了Si O2壳对YVO4∶Eu3+发光性质的影响,结果表明:包覆和未包覆的样品在紫外光激发下都有Eu3+的特征发射;随着Si O2壳厚度的增加,发光强度和量子效率越来越低,Eu3+格位对称性越来越高。     

Ta2O5-PMMA复合栅绝缘层对OFETs性能的影响

选用五氧化二钽（Ta₂O₅）-聚甲基丙烯酸甲酯（PMMA）复合材料作为栅绝缘层制备了并五苯有机场效应晶体管（OFETs）。通过在Ta₂O₅表面旋涂一层PMMA可以降低栅绝缘层的表面粗糙度,增大其场效应晶体管的迁移率。研究了厚度在20~60 nm范围内的PMMA对复合绝缘层表面形貌、粗糙度以及器件电学性能的影响。结果表明,当PMMA厚度为40 nm时,器件的电学性能最佳。与单一的Ta₂O₅栅绝缘层器件相比,其场效迁移率由4.2×10^-2 cm²/（V·s）提高到0.31 cm²/（V·s）;栅电压增加到-20 V时,开关电流比由2.9×10²增大到2.9×10⁵。     

不同钝化结构对非极性AlGaN-MSM紫外探测器性能的提升

在r面蓝宝石衬底上,采用金属有机化学气相沉积（MOCVD）法高温生长了未掺杂非极性AlGaN半导体薄膜,在此基础上制备了金属-半导体-金属（MSM）结构的紫外探测器。系统研究了在AlGaN半导体薄膜表面分别磁控溅射SiO₂纳米颗粒与SiO₂钝化层两种钝化手段对非极性AlGaN-MSM结构的紫外探测器性能的影响。实验结果表明：磁控溅射SiO₂纳米颗粒钝化或SiO₂钝化层两种手段都能提升AlGaN-MSM结构紫外探测器性能。暗电流测试表明,SiO₂纳米颗粒和SiO₂钝化层可使器件暗电流下降1~2个数量级,达到nA量级。光谱响应测试发现,在5 V偏压下,探测器在300 nm处具有陡峭的截止边,这表明其具有很好的深紫外特性,光谱响应提高了10³倍,紫外可见抑制比高达10⁵。     

铟锌氧化物薄膜晶体管局域态分布的提取方法

本文针对铟锌氧化物薄膜晶体管(IZO TFT)的低频噪声特性与变频电容-电压特性展开试验研究,基于上述特性对有源层内局域态密度及其在禁带中的分布进行参数提取.首先,基于IZO TFT的亚阈区I-V特性提取器件表面势随栅源电压的变化关系.基于载流子数随机涨落模型,在考虑有源层内缺陷态俘获/释放载流子效应基础上,通过γ因子提取深能态陷阱的特征温度;基于沟道电流噪声功率谱密度及平带电压噪声功率谱密度的测量,提取IZO TFT有源层内局域态密度及其分布.试验结果表明,带尾态缺陷在禁带内随能量呈e指数变化趋势,其导带底密度N1TA约为3.42×10~(20)cm~(-3)·eV-,特征温度TTA约为135 K.随后,将C-V特性与线性区I-V特性相结合,对栅端寄生电阻、漏端寄生电阻、源端寄生电阻进行提取与分离.在考虑有源层内局域态所俘获电荷与自由载流子的情况下,基于变频C-V特性对IZO TFT有源层内局域态分布进行参数提取.试验结果表明,深能态与带尾态在禁带内随能量均呈e指数变化趋势,深能态在导带底密度NDA约为5.4×10~(15)cm~(-3)·eV~(-1),特征温度TDA约为711 K,而带尾态在导带底密度NTA约为1.99×10~(20)cm~(-3)·eV~(-1),特征温度TTA约为183 K.最后,对以上两种局域态提取方法进行对比与分析.