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A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs 
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下载免费PDF全文 A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD. 相似文献
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为抑制短沟道效应和热载流子效应, 提出了一种非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET新结构. 通过在圆柱坐标系中精确求解三段连续的泊松方程, 推导出新结构的沟道静电势、阈值电压以及亚阈值电流的解析模型. 结果表明, 新结构可有效抑制短沟道效应和热载流子效应, 并具有较小的关态电流. 此外, 分析还表明栅交叠区的掺杂浓度对器件的亚阈值电流几乎没有影响, 而栅电极功函数对亚阈值电流的影响较大. 解析模型结果和三维数值仿真工具ISE所得结果高度符合. 相似文献
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为了研究高介电常数(高k)栅介质材料异质栅中绝缘衬底上的硅和金属-氧化物-硅场效应晶体管的短沟道效应,为新结构器件建立了全耗尽条件下表面势和阈值电压的二维解析模型.模型中考虑了各种主要因素的影响,包括不同介电常数材料的影响,栅金属长度及其功函数变化的影响,不同漏电压对短沟道效应的影响.结果表明,沟道表面势中引入了阶梯分布,因此源端电场较强;同时漏电压引起的电势变化可以被屏蔽,抑制短沟道效应.栅介电常数增大,也可以较好的抑制短沟道效应.解析模型与数值模拟软件ISE所得结果高度吻合.关键词：异质栅绝缘衬底上的硅阈值电压解析模型 相似文献
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Halo structure is added to sub-100 nm surrounding-gate metal-oxide-semiconductor fieldeffect-transistors （MOS- FETs） to suppress short channel effect. This paper develops the analytical surface potential and threshold voltage models based on the solution of Poisson＇s equation in fully depleted condition for symmetric halo-doped cylindrical surrounding gate MOSFETs. The performance of the halo-doped device is studied and the validity of the analytical models is verified by comparing the analytical results with the simulated data by three dimensional numerical device simulator Davinci. It shows that the halo doping profile exhibits better performance in suppressing threshold voltage roll-off and drain-induced barrier lowering, and increasing carrier transport efficiency. The derived analytical models are in good agreement with Davinci. 相似文献
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In this paper, the three-dimensional(3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator(SOI) Fin FETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional(2D) potential model is proposed for the subthreshold region of junctionless SOI Fin FET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted. 相似文献
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This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device. 相似文献
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Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-k gate dielectric 下载免费PDF全文
下载免费PDF全文 By solving Poisson＇s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate （DMSG） metal-oxide semiconductor field-effect transistor （MOSFET） with a high-k gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering （FIBL） on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-k dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator. 相似文献
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The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect. 相似文献
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Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric 下载免费PDF全文
下载免费PDF全文 By solving Poisson’s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal–oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator. 相似文献
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异质栅全耗尽应变硅金属氧化物半导体模型化研究 总被引：1，自引：0，他引：1
为了进一步提高小尺寸金属氧化物半导体(MOSFET)的性能,在应变硅器件的基础上, 提出了一种新型的异质栅MOSFET器件结构.通过求解二维Poisson方程,结合应变硅技术的物理原理,建立了表面势、表面电场以及阈值电压的物理模型,研究了栅金属长度、功函数以及双轴应变对其的影响. 通过仿真软件ISE TCAD进行模拟仿真,模型计算与数值模拟的结果基本符合. 研究表明：与传统器件相比,本文提出的异质栅应变硅新器件结构的载流子输运效率进一步提高, 可以很好地抑制小尺寸器件的短沟道效应、漏极感应势垒降低效应和热载流子效应, 使器件性能得到了很大的提升.关键词：应变硅异质栅阈值电压解析模型 相似文献
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In this paper, we study the effects of an unintended dopant in the channel on the current-voltage char-acteristics of a Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Non-Equilibrium Green's Function (NEGF) approach is used. A quantum transport model to calculate the drain current is presented and subthreshold swing and drain induced barrier lowering (DIBL) effect are studied. 相似文献
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为了避免光照对铟镓锌氧薄膜晶体管(InGaZnO thin film transistors,IGZO TFTs)电学特性的影响,IGZO TFT要增加遮光金属层.本文研究了遮光金属栅极悬浮时,IGZO TFT的输出特性.采用器件数值计算工具TCAD(technology computer-aided design)分析了IGZO层与栅介质层界面处电势分布,证实了悬浮栅(floating gate,FG)IGZO TFT输出曲线的不饱和现象是由悬浮栅与TFT漏端的电容耦合造成.基于等效电容的电压分配方法,提出了悬浮栅IGZO TFT电流的一阶模型.TCAD数值分析及一阶物理模型结果与测试具有较高程度的符合,较完整地解释了悬浮栅IGZO TFT的电学特性. 相似文献
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In this paper, we study the effects of an unintended dopant in the channel on the current-voltage characteristics of a Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Non-Equilibrium Green's Function (NEGF) approach is used. A quantum transport model to calculate the drain current is presented and subthreshold swing and drain induced barrier lowering (DIBL) effect are studied. 相似文献
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This paper proposes an oxide filled extended trench gate superjunction (SJ) MOSFET structure to meet the need of higher frequencypower switches application. Compared with the conventional trenchgate SJ MOSFET, new structure has the smaller input and outputcapacitances, and the remarkable improvements in the breakdownvoltage, on-resistance and switching speed. Furthermore, the SJ in thenew structure can be realized by the existing trench etching andshallow angle implantation, which offers more freedom to SJ MOSFETdevice design and fabrication. 相似文献
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Microfluidic paper-based analytical devices (µPADs) have attracted much attention over the past decade because they offer clinicians the ability to deliver point-of-care testing and onsite analysis. Many of the advantages of µPADs, however, are limited to work in a laboratory setting due to the difficulties of processing data when using electronic devices in the field. This review focuses on the use of µPADs that have the potential to work without batteries or with only small and portable devices such as smartphones, timers, or miniaturized detectors. The µPADs that can be operated without batteries are, in general, those that allow the visual judgment of analyte concentrations via readouts that are measured in time, distance, count, or text. Conversely, a smartphone works as a camera to permit the capture and processing of an image that digitizes the color intensity produced by the reaction of an analyte with a colorimetric reagent. Miniaturized detectors for electrochemical, fluorometric, chemiluminescence, and electrochemiluminescence methods are also discussed, although some of them require the use of a laptop computer for operation and data processing. 相似文献
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By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-kappa gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-kappa dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator. 相似文献
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MOSFET调制器的实验研究 总被引：4，自引：0，他引：4
介绍了MOSFET调制器的基本原理,并对其并联分流和感应叠加两种开关结构进行了实验研究。基于可编辑逻辑器件设计了其触发电路,驱动电路采用高速MOSFET对管组成的推挽输出形式,加快了MOSFET的开关速度。利用Pspice软件对开关上有无剩余电流电路(RCD)两种情况进行仿真,结果表明,加装RCD电路可以有效吸收MOSFET在关断瞬间产生的反峰电压。实验中,电流波形用Pearson线圈测量,用3个MOSFET并联作开关,当电容充电电压为450 V,负载为30 Ω时,脉冲电流13 A,前沿20 ns,平顶约80 ns;用3个单元调制器感应叠加,当电容充电电压为450 A,负载为30 Ω时,脉冲电流强度为40 A,前沿25 ns,平顶约70 ns。 相似文献
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