超薄栅氧化层n-MOSFET软击穿后的导电机制

研究了恒压应力下超薄栅氧化层n型金属-氧化物-半导体场效应晶体管（n-MOSFET）软击穿 后的导电机制.发现在一定的栅电压V_g范围内，软击穿后的栅电流I_g符合Fowl er-Nordheim隧穿公式，但室温下隧穿势垒_b的平均值仅为0936eV，远小于S i/Si O₂界面的势垒高度315eV.研究表明，软击穿后，处于Si/SiO₂界 面量子化能级上的 电子不隧穿到氧化层的导带，而是隧穿到氧化层内的缺陷带上._b与缺陷带能 级和电 子所处的量子能级相关；高温下，激发态电子对隧穿电流贡献的增大导致_b逐 渐降低. 关键词： 软击穿 栅电流 类Fowler-Nordheim隧穿 超薄栅氧化层     

Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

Au/(SiO2/Si/SiO2)纳米双势垒/n+-Si结构的电致发光研究

利用射频磁控溅射方法,在n⁺-Si衬底上淀积SiO₂/Si/SiO_{2纳米双势垒单势阱结构,其中Si层厚度为2至4nm,间隔为0.2nm,邻近n⁺-S i衬底的SiO2层厚度固定为1.5nm,另一SiO2层厚度固定为3nm.为了 对比研究,还制备了Si层厚度为零的结构,即SiO2(4.5nm)/n⁺-Si 结构.在经过600℃氮气下退火30min,正面蒸上半透明Au膜,背面也蒸Au作欧姆接触后,所 有样品都在反向偏置(n^＋-Si的电压高于Au电极的电压)下发光,而在正向偏压 下不发光.在一定的反向偏置下,电流和电致发光强度都随Si层厚度的增加而同步振荡,位 相相同.所有样品的电致发光谱都可分解为相对高度不等的中心位于2.26eV(550nm)和1.85eV (670nm)两个高斯型发光峰.分析指出该结构电致发光的机制是：反向偏压下的强电场使Au/( SiO2/Si/SiO2)纳米双势垒/n⁺-Si结构发生了雪崩击穿 ,产生大量的电子-空穴对,它们在纳米SiO2层中的发光中心(缺陷或杂质)上复 合而发光. 关键词： 电致发光 纳米双势垒 高斯型发光峰 雪崩击穿}     

动态应力下超薄栅氧化层经时击穿的可靠性评价

实验发现动态电压应力条件下,由于栅氧化层很薄,高电平应力时间内隧穿入氧化层的电子与陷落在氧化层中的空穴复合产生中性电子陷阱,中性电子陷阱辅助电子隧穿.由于每个周期的高电平时间较短(远远低于电荷的复合时间),隧穿到氧化层的电子很少,同时低电平应力时间内一部分电荷退陷,形成的中性电子陷阱更少.随着应力时间的累积,中性电子陷阱达到某个临界值,栅氧化层突然击穿.高电平时形成的陷阱较少和低电平时一部分电荷退陷,使得器件的寿命提高. 关键词： 超薄栅氧化层 斜坡电压 经时击穿     

超薄栅下LDD nMOSFET器件GIDL应力下退化特性

对1.4nm超薄栅LDD nMOSFET器件栅致漏极泄漏GIDL(gate-induced drain leakage)应力下的阈值电压退化进行了研究.GIDL应力中热空穴注进LDD区界面处并产生界面态，这导致器件的阈值电压变大.相同栅漏电压V_DG下的不同GIDL应力后阈值电压退化量的对数与应力V_D/V_DG的比值成正比.漏偏压V_D不变的不同GIDL应力后阈值电压退化随着应力中栅电压的增大而增大，相同栅偏压V_G下的不同GIDL应力后阈值电压退化也随着应力中漏电压的增大而增大，这两种应力情形下退化量在半对数坐标下与应力中变化的电压的倒数成线性关系，它们退化斜率的绝对值分别为0.76和13.5.实验发现器件退化随着应力过程中的漏电压变化远大于随着应力过程中栅电压的变化. 关键词： 栅致漏极泄漏 CMOS 阈值电压 栅漏电压     

恒流应力下E2PROM隧道氧化层的退化特性研究

在电容测量的基础上研究了薄隧道氧化层在恒定Fowler-Nordheim(F-N)隧穿电流下的退化情况. 这种退化是恒流应力和时间的函数，对恒流应力大小的依赖性更加强烈，隧道氧化层在F-N电流下的退化是注入电荷密度(Q_inj)的函数. 在较低Q_inj下氧化层中发生正电荷俘获，在较高Q_inj下发生负电荷俘获，导致栅压变化的反复. 关键词： 2PROM')" href="#">E²PROM 隧道氧化层 退化 恒流应力     

薄栅氧化层经时击穿的参数表征研究

在恒压应力条件下测试了薄栅氧化层的击穿特性,研究了TDDB的击穿机理,讨论了栅氧化层面积对击穿特性的影响.对击穿电荷Q_BD进行了实验测试和分析,结果表明：击穿电荷Q_BD不是常数,它依赖栅氧化层面积和栅电压.对相关系数进行了拟合,给出了Q_BD的解析表达式. 关键词：     

具有HfN/HfO2栅结构的p型MOSFET中的负偏置-温度不稳定性研究

研究了HfN/HfO₂高K栅结构p型金属-氧化物-半导体(MOS)晶体管(MOSFET)中，负 偏置-温度应力引起的阈值电压不稳定性(NBTI)特征.HfN/HfO₂高K栅结构的等效 氧化层厚度(EOT)为1.3nm，内含原生缺陷密度较低.研究表明，由于所制备的HfN/HfO₂ 高K栅结构具有低的原生缺陷密度，因此在p-MOSFET器件中观察到的NBTI属HfN/HfO2高K栅结构的本征特征，而非工艺缺陷引起的；进一步研究表明，该HfN/HfO₂高K栅结构中观察到的NBTI与传统的SiO₂基栅介质p-MOSFET器件中观察 到的NBTI具有类似的特征，可以被所谓的反应-扩散(R-D)模型表征： HfN/HfO₂ 栅结构p-MOSFET器件的NBTI效应的起源可以归为衬底注入空穴诱导的界面反应机理，即在负 偏置和温度应力作用下，从Si衬底注入的空穴诱导了Si衬底界面Si-H键断裂这一化学反应的 发生，并由此产生了Si^＋陷阱在Si衬底界面的积累和H原子在介质层内部的扩散 ，这种Si^＋陷阱的界面积累和H原子的扩散导致了器件NBTI效应的发生. 关键词： 高K栅介质 负偏置-温度不稳定性(NBTI) 反应-扩散(R-D)模型     

金属氧化物半导体场效应管热载流子退化的1/fγ噪声相关性研究

研究了金属氧化物半导体(MOS)器件在高、中、低三种栅压应力下的热载流子退化效应及其1/f^γ噪声特性.基于Si/SiO₂界面缺陷氧化层陷阱和界面陷阱的形成理论,结合MOS器件1/f噪声产生机制,并用双声子发射模型模拟了栅氧化层缺陷波函数与器件沟道自由载流子波函数及其相互作用产生能级跃迁、交换载流子的具体过程.建立了热载流子效应、材料缺陷与电参量、噪声之间的统一物理模型.还提出了用噪声参数Sf ^{关键词： 金属氧化物半导体场效应管 热载流子 fγ噪声')" href="#">1/fγ噪声}     

Al2O3介质层厚度对AlGaN/GaN金属氧化物半导体-高电子迁移率晶体管性能的影响

在蓝宝石衬底上采用原子层淀积法制作了三种不同Al₂O₃介质层厚度的绝缘栅高电子迁移率晶体管.通过对三种器件的栅电容、栅泄漏电流、输出和转移特性的测试表明：随着Al₂O₃介质层厚度的增加,器件的栅控能力逐渐减弱,但是其栅泄漏电流明显降低,击穿电压相应提高.通过分析认为薄的绝缘层能够提供大的栅电容,因此其阈值电压较小,但是绝缘性能较差,并不能很好地抑制栅电流的泄漏;其次随着介质厚度的增加,可以对栅极施加更高的正偏压,因此获 关键词： 2O₃')" href="#">Al₂O₃ 金属氧化物半导体-高电子迁移率晶体管 介质层厚度 钝化     

高场应力及栅应力下AlGaN/GaN HEMT器件退化研究

采用不同的高场应力和栅应力对AlGaN/GaN HEMT器件进行直流应力测试,实验发现：应力后器件主要参数如饱和漏电流,跨导峰值和阈值电压等均发生了明显退化,而且这些退化还是可以完全恢复的;高场应力下,器件特性的退化随高场应力偏置电压的增加和应力时间的累积而增大;对于不同的栅应力,相对来说,脉冲栅应力和开态栅应力下器件特性的退化比关态栅应力下的退化大.对不同应力前后器件饱和漏电流,跨导峰值和阈值电压的分析表明,AlGaN势垒层陷阱俘获沟道热电子以及栅极电子在栅漏间电场的作用下填充虚栅中的表面态是这些不同应 关键词： AlGaN/GaN HEMT器件 表面态(虚栅) 势垒层陷阱 应力     

Degradation and recovery properties of AlGaN/GaN high-electron mobility transistors under direct current reverse step voltage stress

Direct current (DC) reverse step voltage stress is applied on the gate of AlGaN/GaN high-electron mobility transistor (HEMT). Experiments show that parameters degenerate under stress. Large-signal parasitic source/drain resistance (R_S/R_D) and gate-source forward I-V characteristics are recoverable after breakdown of the device under test (DUT). Electrons trapped by both the AlGaN barrier trap and the surface state under stress lead to this phenomenon, and surface state recovery is the major reason for the recovery of device parameters.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al₂O₃ as the gate dielectric, deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8⁰N-/N+ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties (1×10¹⁴ cm^-2) and low gate-leakage current (I_G = 1 × 10^-3 A/cm^-2@E_ox = 8 MV/cm). Analysis of the current conduction mechanism on the deposited Al₂O₃ gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.     

高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD) SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-kappa gate dielectric

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-kappa gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-kappa dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

增强型AlGaN/GaN高电子迁移率晶体管高温退火研究

深入研究了两种增强型AlGaN/GaN高电子迁移率晶体管(HEMT)高温退火前后的直流特性变化.槽栅增强型AlGaN/GaN HEMT在500 ℃ N₂中退火5 min后,阈值电压由0.12 V正向移动到0.57 V,器件Schottky反向栅漏电流减小一个数量级.F注入增强型AlGaN/GaN HEMT在 400 ℃ N₂中退火2 min后,器件阈值电压由0.23 V负向移动到-0.69 V,栅泄漏电流明显增大.槽栅增强型器件退火过程中Schottky有效势垒     

微晶硅薄膜晶体管稳定性研究

对有源区处于结构过渡区的微晶硅底栅薄膜晶体管，测试其偏压衰退特性时，观察到一种“自恢复”的衰退现象.当栅和源漏同时施加10 V的偏压时，测试其源-漏电流随时间的变化，发现源-漏电流先衰减、而后又开始恢复上升的反常现象.而当采用栅压为10 V、源-漏之间施加零偏压的模式时，源-漏电流随时间呈先是几乎指数式下降、随之是衰退速度减缓的正常衰退趋势.就此现象进行了初步探讨. 关键词： 过渡区硅材料 微晶硅薄膜晶体管 稳定性 自恢复衰退     

XOR gate response in a mesoscopic ring with embedded quantum dots

We address XOR gate response in a mesoscopic ring threaded by a magnetic flux . The ring, composed of identical quantum dots, is symmetrically attached to two semi-infinite one-dimensional metallic electrodes and two gate voltages, viz, V_a and V_b, are applied, respectively, in each arm of the ring which are treated as the two inputs of the XOR gate. The calculations are based on the tight-binding model and the Green’s function method, which numerically compute the conductance–energy and current–voltage characteristics as functions of the ring-electrodes coupling strengths, magnetic flux and gate voltages. Quite interestingly it is observed that, for =₀/2 (₀=ch/e, the elementary flux-quantum) a high output current (1) (in the logical sense) appears if one, and only one, of the inputs to the gate is high (1), while if both inputs are low (0) or both are high (1), a low output current (0) appears. It clearly demonstrates the XOR behavior and this aspect may be utilized in designing the electronic logic gate.