A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

低功耗CMOS低噪声放大器的设计

针对低功耗电路设计的需求,提出了一种低功耗约束下CMOS低噪声放大器的设计方法,并与传统的设计方法进行了对比。模拟结果表明,按照该方法基于0.18μm CMOS工艺设计的工作于1.58 GHz的低噪声放大器,在仅消耗1.9 mA电流的条件下,噪声指数小于1 dB。     

一种2.4 GHz CMOS射频前端电路

基于0.18 μm CMOS工艺,设计了一种面向低速率低功耗应用的2.4 GHz射频前端电路,包含2个单刀双掷开关、1个功率放大器和1个低噪声放大器。采用栅衬浮动电压偏置技术对传统单刀双掷开关进行了改进,以提高其线性度;功率放大器采用两级放大结构,对全集成的低噪声放大器进行了噪声优化;集成了输入输出匹配网络,采用了到地电感,以提高输入输出端的ESD性能。在接收模式时,电路的静态电流为10.7 mA,增益为11.7 dB,IIP3为2.1 dBm,噪声系数为3.4 dB。在发射模式时,电路的静态电流为17.4 mA,功率增益为17.7 dB,输出P1dB为20 dBm,饱和功率为21.4 dBm,最大PAE为23.8%,在输出功率为20 dBm时的频谱满足802.15.4协议要求。     

UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

In this work, design and measurement results of UHF RF frontend circuits to be used in low-IF and subsampling receiver architectures are presented. We report on three low noise amplifiers (LNA) (i) single-ended (ii) differential (iii) high-gain differential and a double-balanced mixer all implemented in 0.35-μ m SOI (Silicon on Insulator) CMOS technology of Honeywell. These circuits are considered as candidate low-power building blocks to be used in the two fully-integrated receiver chips targeted for deep space communications. Characteristics of square spiral inductors with high quality (Q) factors (as high as 10.8) in SOI CMOS are reported. Single-ended and fully-differential LNA's provide gains of 17.5 dB and 18.74 dB at 435 MHz, respectively. Noise figure of the single-ended LNA is 2.91 dB while the differential LNA's noise figure is 3.25 dB. These results were obtained for the power dissipations of 12.5 mW and 16.5 mW from a 2.5-V supply for the single-ended and differential LNA's, respectively. High-gain low-power differential LNA provides a small-signal gain of 45.6 dB with a noise figure of 2.4 dB at 435 MHz. Total power dissipation of the high gain LNA is 28 mW from a 3.3-V supply. The double-balanced mixer provides a conversion gain of 5.5 dB with a noise figure of 13 dB at 2 MHz IF. The power dissipation of the mixer is 11.5 mW from a 2.5-V supply. The measured responses and the power dissipations of the building blocks meet the requirements of the communications system. The die areas occupied by the single-ended LNA, differential LNA, high-gain LNA and the mixer are 0.6 mm × 1.4 mm, 1 mm × 1.4 mm, 1.4 mm × 1.2 mm and 0.6 mm × 0.9 mm, respectively. Ertan Zencir received the B.Sc. and M.S. degrees in electrical and electronics engineering from Middle East Technical University, Ankara, Turkey, and Ph.D. degree in electrical engineering from Syracuse University, Syracuse, NY in 1995, 1997, and 2003, respectively. He joined the Electrical Engineering and Computer Science Department of University of Wisconsin-Milwaukee as an Assistant Professor in August 2004. 2003). His current research focuses on RFIC and transceiver design for wireless communications. Douglas Te-Hsin Huang was born in Chia-yi Taiwan. He received the B.S. degree in electrical engineering from National Taiwan Ocean University, Kee-lung, Taiwan in 1993, and the M.S. and Ph.D. degrees in electrical engineering from Syracuse University, Syracuse, New York, in 2001 and 2003, respectively. In 2004, he joined Skyworks Solutions Inc., where he is currently an RFIC Design Engineer. His research deals mainly with low-power, infrastructure, analog RFIC, and microwave integrated circuit designs. Besides microwave and semiconductor engineering, Dr. Huang has broad interest in art, music, and philosophy. Ahmet Tekin received his B.S. degree in Electrical Engineering from Bogazici University, Istanbul, Turkey in 2002 and MS degree in Electrical engineering form North Carolina A&T State University, Greensboro, NC. He is currently working towards his PhD degree at University of California, Santa Cruz, CA. He was a Research Assistant at RF Microelectronic Laboratory, North Carolina A&T State University, from 2002 to 2004. He worked on the design of low power UHF transceiver circuits for space applications. He is currently a Research Assistant at Bio-mimetic Microelectronic Systems Laboratory, University of California at Santa Cruz, working on implantable very low power UHF frequency transceiver for a body sensor network. Numan S. Dogan received the B.Sc. degree from Karadeniz Technical University, Trabzon, Turkey, in 1975, the M.Sc. degree from Polytechnic University, New York, in 1979, and the PhD degree from the University of Michigan, Ann Arbor, in 1986, all in electrical engineering. Since 1998, he has been with the Electrical and Computer Engineering Department, North Carolina A&T State University, Greensboro, North Carolina, where he is an Associate Professor. He was a Visiting Faculty Researcher at Air Force Research Laboratory (AFRL), Eglin Air Force Base, Florida, in 1998, and General Electric Corporate Research and Development Laboratory, Schenectady, New York, in 1999. His earlier research interests included microwave and millimeter-wave solid-state devices and circuits, high-temperature electronics, and silicon micromachining. His recent research interests include RF CMOS Integrated Circuits and low-power Medical Implant Communication Systems (MICS) transceivers. Currently he serves as the Chair of the IEEE Central North Carolina Section. In April 2004, he organized “a walking robot competition” for High School Students. He enjoys hiking to Alpine Lakes in the Pacific Northwest and fishing. Ercument Arvas (M'85–SM'89) received the B.S. and M.S. degrees from METU, Ankara, Turkey, in 1976 and 1979, respectively, and the Ph.D. degree from Syracuse University, Syracuse, New York, in 1983, all in Electrical Engineering. Between 1984 and fall of 1987, he was with the Electrical Engineering Department of Rochester Institute of Technology, Rochester, New York. He joined the Electrical Engineering and Computer Science Department of Syracuse University in 1987, where he is currently a Professor. His research interests include numerical electromagnetics, antennas, and microwave circuits and devices.     

低功耗高增益CMOS LNA的设计

设计了一种完全可以单片集成的低功耗高增益CMOS低噪声放大器(LNA).所有电感都采用片上螺旋电感,并实现了片上50 Ω的输入阻抗匹配.文中设计的放大器采用TSMC0.18 μmCMOS工艺,用HSPICE模拟软件对其进行了仿真,并进行了流片测试.结果表明,所设计的低噪声放大器结构简单,极限尺寸为0.18 μm,当中心频率fo为2.4 GHz、电源电压VDD为1.8 V时其功率增益S21为16.5 dB,但功耗Pd只有2.9 mW,噪声系数NF为2.4 dB,反向隔离度S12为-58 dB.由此验证了所设计的CMOS RF放大器可以在满足低噪声、低功耗、高增益的前提下向100 nm级的研发方向发展.     

Two CMOS LNAs Sharing the Same On-Chip Inductors and Bias Network

An area-efficient design for two 2.4 GHz CMOS LNAs is presented, by sharing the on-chip inductors and bias network. Compared with LNA1, LNA2 features a new technique to improve the linearity of CMOS LNA, achieving a much higher IIP3 with the tradeoff of voltage gain and noise figure.     

CMOS射频集成电路的研究进展

近年来，射频集成电路(RFIC)的应用和研究得到了飞速的发展，CMOS射频IC的研究更是成为该领域的研究重点和热点。文章对CMOS技术在射频和微波领域的应用进行了详细的探讨，着重介绍了当前射频通讯中常用的收发机结构及其存在的问题和解决方案；分析了射频收发机前端关键电路模块低噪声放大器(LNA)、混频器(Mixer)、压控振荡器(VCO)、功率放大器(PA)和射频关键无源元件的最新研究进展；展望了CMOS技术在射频领域的发展前景。     

1GHz 0.5μm CMOS低噪声放大器的设计

从低噪声放大器(L NA)的设计原理出发,提出并设计了一种工作于1GHz的实用L NA.电路采用共源-共栅的单端结构,用HSPICE软件对电路进行分析和优化.模拟过程中选用的器件采用TSMC0 .5 μm CMOS工艺实现.模拟结果表明所设计的L NA功耗小于15 m W,增益大于10 d B,噪声系数为1.87d B,IIP3大于10 d Bm,输入反射小于- 5 0 d B.可用于1GHz频段无线接收机的前端     

CMOS 射频低噪声放大器的设计

讨论了CMOS射频低噪声放大器的相关设计问题,对影响其增益、噪声系数、线性度等性能指标的因素进行了分析,并综述了几种提高其综合性能指标的方法。在此基础上,采用SMIC0．25μm CMOS工艺库,给出了3．8GHz CMOSLNA的设计方案。HSPICE仿真结果表明：电路的功率增益为13．48dB,输入、输出匹配良好,噪声系数为2．9dB,功耗为46．41mw。     

0.13微米CMOS双通道超宽带低噪声放大器设计

本文设计了一款超宽带低噪声放大器,并对设计流程进行分析仿真.该低噪放采用双通道结构,有效的输入阻抗匹配、平稳的增益和低噪声等性能可以同时实现.应用ADS工具TSMC 0.13μm CMOS工艺库的仿真结果表明,其最大功率增益为14.2dB,在8GHz频点的IIP3为-4dBm,输入、输出反射系数分别小于-10.2dB和-10.89dB,噪声指数单调下降到1.46dB,并且总功耗和带内最大增益摆幅较低.     

CMOS single-ended-to-differential low-noise amplifier

In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to minimize power consumption, active loads and currents mirrors have been replaced by optimized inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode S-parameters. The LNA has been implemented using a 0.35 μm RFCMOS technology. Performances are a noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180±1°. Regarding non-linear behaviour, the obtained 1 dB-compression point obtained is −9.5 dB m while intermodulation intercept point is −3 dB m, dissipating 6 mA from 1.5 V supply voltage.     

On the use of body biasing to improve linearity in low LO-power CMOS active mixers

In a radio-frequency (RF) transceiver, the linearity of the mixer has a profound effect on the overall transceiver performance. In many RF transceivers, active mixers are used due to their higher gain which also improves the overall receiver noise figure. In a typical RF active mixer where the transistors in the LO stage switch abruptly, most of the nonlinear distortions come from the transconductance or RF stage and thus the linearity of the mixer can be enhanced by proper design of the RF stage. In low-power receivers, however, to reduce the power consumption of the local oscillator (LO) circuit, the amplitude of LO signal is low and thus the switching of the transistors in the LO stage of the mixer is gradual. In this paper, we propose a technique to improve the linearity of such low-power mixers by enhancing the linearity of the LO stage. In particular, body biasing is utilized in the LO stage to improve the linearity. To verify the effectiveness of the proposed technique, two proof-of-concept double-balanced down-conversion active mixers have been designed and fabricated in 0.13-µm CMOS. The maximum IIP3 of +2.7 dBm and −4.9 dBm at a conversion gain of 13 dB and 16 dB are achieved for the first and second prototype respectively. For a 2.4 GHz RF input signal and an intermediate-Frequency (IF) of 50 MHz, the first prototype consumes 2.4 mW from a 1.2 V supply while the second one consumes only 780 µW from a 0.7 V supply.     

应用于智能水表的低功耗低噪声放大器设计

提出了基于多管并联结构的低功耗低噪声放大器(LNA),讨论了这种结构下噪声与功耗的相互关系,提出了低功耗LNA基于优化区概念的设计准则.提出的电路具有结构简单对称的特点.在0.35 μm CMOS工艺下进行PSPICE仿真测试.结果表明,新的低噪声放大器在(2.5) V电压下功耗仅为110 μW,等效输入噪声为16.5 nV/Hz~(1/2).与已发表的低噪声放大器比较,具有明显的低功耗特点.     

A 3.3 V Power Feedback Chip for Linearization of RF Power Amplifiers

The power feedback technique is a simple and low cost linearization scheme suitable for consumer products such as hand sets. This paper presents a custom chip for linearization of RF power amplifiers using power feedback. The chip, implemented in a standard double-metal double-poly 0.6 m CMOS process, operates with 3.3 V supply voltage and consumes 62 mW. When it was used to linearize a commercially available high efficiency RF power amplifier at 850 MHz, experimental results showed that out-of-band power at 30 kHz offset was reduced some 10 dB for a /4-shifted DQPSK modulated North American digital cellular (NADC) signal. For the same level of adjacent channel interference (ACI), the efficiency was increased from 35% to 48%.     

CMOS低噪声放大器中的输入匹配研究与设计

分析了低噪声放大器设计中最常用的源极电感负反馈输入匹配结构,指出其存在的缺陷及如何改进,即利用一个小值LC网络代替大感值的栅极电感Lg,同时移除源极负反馈电感Ls.应用这种改进型输入匹配结构,基于0.18μm BSIM3模型设计了工作频带为5.1～5.8 GHz的宽带CMOS低噪声放大器.结果表明,虽然输入匹配由于移除源极负反馈电感Ls受到一定影响,但是有利于降低噪声系数并减小实际制作的芯片面积.     

2.45 GHz全集成CMOS功率放大器设计

在一个RF收发机系统中,功率放大器的集成问题一直是难点之一.首先简要介绍开关模式功率放大器及其提高效率的理论基础,然后采用0.18 μm CMOS工艺给出了工作在2.45 GHz的全集成单片功率放大器的设计,并采用ADS仿真软件验证了设计的正确性.     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

4·2GHz CMOS射频前端电路设计

设计并实现了一个工作在4.2 GHz的全集成CMOS射频前端电路,包括可实现单端输入到差分输出变换的低噪声放大器和电流注入型Gilbert有源双平衡混频器.电路采用SMIC 0.18 μm RF工艺.测试结果表明,在1.8 V电源电压下,电路的功率增益可达到26 dB,1 dB压缩点为-27 dBm,电路总功耗 (含Buffer) 为21 mA.