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基于0.18 μm CMOS工艺,设计了一种面向低速率低功耗应用的2.4 GHz射频前端电路,包含2个单刀双掷开关、1个功率放大器和1个低噪声放大器。采用栅衬浮动电压偏置技术对传统单刀双掷开关进行了改进,以提高其线性度;功率放大器采用两级放大结构,对全集成的低噪声放大器进行了噪声优化;集成了输入输出匹配网络,采用了到地电感,以提高输入输出端的ESD性能。在接收模式时,电路的静态电流为10.7 mA,增益为11.7 dB,IIP3为2.1 dBm,噪声系数为3.4 dB。在发射模式时,电路的静态电流为17.4 mA,功率增益为17.7 dB,输出P1dB为20 dBm,饱和功率为21.4 dBm,最大PAE为23.8%,在输出功率为20 dBm时的频谱满足802.15.4协议要求。 相似文献
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A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 load. A design method to find the large signal parameters of the output transistor is presented. It separates the determination of the optimal load resistance and the determination of the large signal drain-source capacitance. Based on this method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA is proposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of the spectral leakage and the error vector magnitude of a EDGE (3/8-8PSK) modulated signal. 相似文献
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设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59~64 GHz的微波信号下变频至5~10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5~17.5 dB,双边带噪声因子为6.4~7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。 相似文献
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射频功率放大器是无线设备的关键器件,GaAs工艺被广泛使用在射频功放的设计制造上。而CMOS工艺在生产成熟度和成本上有很大优势,主要关注用CMOS工艺来做射频功放的问题,介绍世界上第一颗量产的CMOS功放及其所使用的特殊技术。利用一款成熟的手机产品,替换这颗功放及外围器件,最后与原产品进行对比测试。 相似文献
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S. Toofan A.R. Rahmati A. Abrishamifar G. Roientan Lahiji 《Microelectronics Journal》2007,38(12):1150-1155
In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of Cgd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S21), high reverse isolation (S12)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply. 相似文献
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设计了一种完全可以单片集成的低功耗高增益CMOS低噪声放大器(LNA).所有电感都采用片上螺旋电感,并实现了片上50 Ω的输入阻抗匹配.文中设计的放大器采用TSMC0.18 μmCMOS工艺,用HSPICE模拟软件对其进行了仿真,并进行了流片测试.结果表明,所设计的低噪声放大器结构简单,极限尺寸为0.18 μm,当中心频率fo为2.4 GHz、电源电压VDD为1.8 V时其功率增益S21为16.5 dB,但功耗Pd只有2.9 mW,噪声系数NF为2.4 dB,反向隔离度S12为-58 dB.由此验证了所设计的CMOS RF放大器可以在满足低噪声、低功耗、高增益的前提下向100 nm级的研发方向发展. 相似文献
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E. Garcia-Moreno Author Vitae K. Suenaga Author VitaeAuthor Vitae S. Bota Author VitaeAuthor Vitae E. Isern Author Vitae 《Integration, the VLSI Journal》2009,42(1):95-102
In this paper, we present two built-in self-test strategies for the down-converter stage in a GSM receiver. These strategies are based on the prediction of its performance parameters from measurements in test mode. By reusing some receiver blocks as part of the test set-up, the circuitry overhead is kept small. The first strategy uses the local oscillator (LO) signal as the only test stimuli. The second strategy uses additional test circuitry, a generator, and an auxiliary mixer. Prediction accuracies are similar in both strategies, but the test observables in the second one are easier to be obtained. 相似文献
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An area-efficient design for two 2.4 GHz CMOS LNAs is presented, by sharing the on-chip inductors and bias network. Compared with LNA1, LNA2 features a new technique to improve the linearity of CMOS LNA, achieving a much higher IIP3 with the tradeoff of voltage gain and noise figure. 相似文献
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提出了一种紧凑的射频互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)放大器LC输出匹配电路,利用放大器漏极偏置电感、输出端隔直电容与放大器输出端并联电感电容形成高阶LC谐振网络,可在占用较小芯片面积的条件下实现较传统L型匹配电路更宽频率范围的输出阻抗匹配。推导了该LC输出匹配电路元件值的计算式,并根据提出的设计方法,采用65 nm CMOS工艺设计了一款K频段放大器,其输出匹配电路尺寸仅98 μm ×150 μm。仿真结果表明,在16.5~22.1 GHz频率范围内放大器的玈22<-10 dB,阻抗匹配带宽相比L型匹配电路增加166%。放大器实测S参数和仿真结果相符,验证了该LC匹配电路可实现紧凑的宽带阻抗匹配。 相似文献
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Tomás Carrasco Carrillo Author Vitae José Gabriel Macias-Montero Author VitaeAuthor Vitae Javier Sieiro Córdoba Author VitaeAuthor Vitae 《Integration, the VLSI Journal》2009,42(3):304-311
In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to minimize power consumption, active loads and currents mirrors have been replaced by optimized inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode S-parameters. The LNA has been implemented using a 0.35 μm RFCMOS technology. Performances are a noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180±1°. Regarding non-linear behaviour, the obtained 1 dB-compression point obtained is −9.5 dB m while intermodulation intercept point is −3 dB m, dissipating 6 mA from 1.5 V supply voltage. 相似文献
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Patrick Reynaert Koen Mertens Michiel Steyaert 《Analog Integrated Circuits and Signal Processing》2002,32(2):177-182
Today, there is a trend towards integration of complex RF systems on a single die. The interaction between the different building blocks will cause a performance degradation of each individual building block. So, optimizing the performance of the total system is under discussion. When combining a CMOS power amplifier together with an up-conversion mixer, some pre-amplifier stages have to be placed between the mixer and the CMOS power transistor. How this stages have to be designed (sized) and how they affect the performance of the power amplifier, will be investigated in this paper. 相似文献
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Per Madsen Jan Hvolgaard Mikkelsen Jens Christian Lindof Torben Larsen 《Analog Integrated Circuits and Signal Processing》2006,46(1):47-55
This paper investigates a Q-enhanced LC resonator implemented with a Q-enhancement circuit based on both active and reactive
components. An analytical expression is presented for the Q-enhancement circuit and simulations are compared with measurements
on a differential Q-enhanced LC tank operating at 1779–1870 MHz. Sensitive circuits and inaccurate models leads to inaccurate
simulations. To improve the accuracy of simulations, S-parameter measurements of components and sub-circuits are included
in the simulations whereby an accuracy of 3 MHz in the estimate of the resonator center frequency results.
Per Madsenreceived his M.Sc.E.E degree in 1997 from Aalborg University, Denmark. In 2005 he received his Industrial PhD degree, also
from Aalborg University. He is currently working with development of reference designs for GSM and UMTS at Texas Instruments
Denmark A/S.
Jan Hvolgaard Mikkelsenreceived his M.Sc.E.E. degree in 1995 from Aalborg University, Denmark. In 2005 he received his PhD degree, also from Aalborg
University. He is currently employed as an Assistant Professor at Aalborg University where he is working as an IC design manager
for the large scale RF IC design efforts at Aalborg University. His research interests include both RF and LF CMOS design
as well as transceiver architectures.
Jens Christian Lindofreceived his M.Sc.E.E. degree in electrical engineering in 1991 from Aalborg University, Denmark, in 1991. He is currently
R&D Director at Texas Instruments Denmark A/S, where he is responsible for all HW and SW developed for Texas Instrument's
cellular reference designs for GSM, GPRS, EDGE and UMTS.
Torben Larsenreceived his M.Sc.E.E. degree in electrical engineering from Aalborg University, Denmark, in 1988, and the Dr. Techn. degree
from Aalborg University in 1998. He has been employed as full Professor at Aalborg University since 2001. Dr. Larsen serves
as reviewer for IEE, IEEE and Wiley. Areas of specialized research interests include noise theory, nonlinear analysis techniques,
RF techniques, RF CMOS technology, and digital modulation techniques. 相似文献
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介绍了RF SOI CMOS技术的特点。着重论述了RF SOI CMOS技术的低串扰特性、低损耗特性及其优质无源元件的性能。最后,阐述了RF SOI CMOS技术在RF系统片上集成方面的应用情况。 相似文献
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采用SMIC 180 nm工艺,设计了一种地端关断差分驱动CMOS射频整流器。通过切断能量传输路径,解决了传统可关断差分驱动CMOS射频整流器因短路电流较高导致关断功耗(POFF)较大的问题。搭建可重构3阶整流电路,验证该射频整流器的功能。仿真结果表明,相对于传统可关断差分驱动CMOS射频整流器,当输入电压VIN幅值为1 V、负载电阻RL为10 kΩ时,在零电压关断的情况下,该整流器的POFF下降了15.2 dBm @953 MHz;在负电压关断情况下,POFF下降了24.5 dBm @953 MHz。该整流器满足射频能量收集系统中整流器低功耗待机的要求。 相似文献