On graphs preserving rectilinear shortest paths in the presence of obstacles

In physical VLSI design, network design (wiring) is the most time-consuming phase. For solving global wiring problems, we propose to first compute from the layout geometry a graph that preserves all shortest paths between pairs of relevant points, and then to operate on that graph for computing shortest paths, Steiner minimal tree approximations, or the like. For a set of points and a set of simple orthogonal polygons as obstacles in the plane, withn input points (polygon corner or other) altogether, we show how a shortest paths preserving graph of sizeO(n logn) can be computed in timeO(n logn) in the worst case, with spaceO(n). We illustrate the merits of this approach with a simple example: If the length of a longest edge in the graph is bounded by a polynomial inn, an assumption that is clearly fulfilled for graphs derived from VLSI layout geometries, then a shortest path can be computed in timeO(n logn log logn) in the worst case; this result improves on the known best one ofO(n(logn)^3/2).     

Guided Local Search for Final Placement in VLSI Design

The design of a VLSI circuit consists of two main parts: First, the logical functionality of the circuit is described, and then the physical layout of the modules and connections is settled. In the latter process one wishes to place the modules such that the necessary wiring becomes as small as possible in order to minimize area usage and delays on signal paths. The placement problem is the subproblem of the layout problem which considers the geometric locations of the modules. A new heuristic is presented for the general cell placement problem where the objective is to minimize total bounding box netlength. The heuristic is based on the Guided Local Search (GLS) metaheuristic. GLS modifies the objective function in a constructive way to escape local minima. Previous attempts to use local search on final (or detailed) placement problems have often failed as the neighbourhood quickly becomes too excessive for large circuits. Nevertheless, by combining GLS with Fast Local Search it is possible to focus the search on appropriate sub-neighbourhoods, thus reducing the time complexity considerably. Comprehensive computational experiments with the developed algorithm are reported on a broad range of industrial circuits. The experiments demonstrate that the developed algorithm is able to improve the estimated routing length of large-sized layouts with as much as 20 percent when compared to existing algorithms.     

Locally minimal uniformly oriented shortest networks

The Steiner problem in a λ-plane is the problem of constructing a minimum length network interconnecting a given set of nodes (called terminals), with the constraint that all line segments in the network have slopes chosen from λ uniform orientations in the plane. This network is referred to as a minimum λ-tree. The problem is a generalization of the classical Euclidean and rectilinear Steiner tree problems, with important applications to VLSI wiring design.A λ-tree is said to be locally minimal if its length cannot be reduced by small perturbations of its Steiner points. In this paper we prove that a λ-tree is locally minimal if and only if the length of each path in the tree cannot be reduced under a special parallel perturbation on paths known as a shift. This proves a conjecture on necessary and sufficient conditions for locally minimal λ-trees raised in [M. Brazil, D.A. Thomas, J.F. Weng, Forbidden subpaths for Steiner minimum networks in uniform orientation metrics, Networks 39 (2002) 186-222]. For any path P in a λ-tree T, we then find a simple condition, based on the sum of all angles on one side of P, to determine whether a shift on P reduces, preserves, or increases the length of T. This result improves on our previous forbidden paths results in [M. Brazil, D.A. Thomas, J.F. Weng, Forbidden subpaths for Steiner minimum networks in uniform orientation metrics, Networks 39 (2002) 186-222].     

A deep-submicron steiner tree

An A-Tree is a rectilinear Steiner tree in which every sink is connected to a driver by a shortest length path, while simultaneously minimizing total wire length. This paper presents a polynomial approximation algorithm for the generalized version of an A-Tree problem with upper-bounded delays along each path from the driver to the sinks and with restrictions on the number of Steiner nodes. We refer to it as “Deep-submicron Steiner tree”, as minimizing the number of Steiner nodes is crucial for signal integrity issues in deep-submicron Very-Large-Scaled-Integrated-circuit (VLSI) designs. The idea behind the algorithm is to control two parameters in order to construct a feasible (with respect to the paths delays and the number of Steiner nodes) tree of small cost.The simulation results show the high efficiency of our approach.     

On Using Tabu Search for Design Automation of VLSI Systems

Tabu search is a meta-heuristic problem solving technique that, when applied carefully, provides near optimal solutions in a very short time. In this paper, we have described the use of tabu search for solving problems related to very large scale integrated (VLSI) circuit design automation. Specifically, we have demonstrated the use for VLSI circuit partitioning and placement. We present a tabu search based circuit bi-partitioning technique that partitions circuits with the goal of minimizing the size of the cutset between the partitions. Then, we use tabu search techniques along with force directed placement techniques to accomplish the physical placement of VLSI circuits on regular two-dimensional arrays with the goal of minimizing the placement time. We use empirical data from partitioning and placement of benchmark circuits to test our techniques. Our methods show improvement when compared to partitioning techniques from the literature and commercially available placement tools. Relative to the literature, our tabu search bi-partitioning technique improves on the best known minimum cuts for several benchmark circuits. Relative to commercially available computer aided design tools, our tabu search based placement approach shows dramatic (20×) speedup in execution time without negative impact on the quality of the solution.     

An explicit approach for time-optimal trajectory planning for kinematically redundant serial robots

Kinematically redundant serial robots have become industrially important due their increased workspace and their inherent capability of null space motion resulting in remarkable adaptiveness to specific tasks compared to conventional, non-redundant manipulators. Attempting to increase the cost-effectiveness of industrial processes, introducing minimum-time trajectories may yield economical advantages due to reduced motion cycle times. This contribution presents a method that uses joint space decomposition and analytic inverse kinematics as well as standard optimization techniques to obtain minimum-time B-spline joint trajectories along prescribed task space paths for kinematically redundant serial robots. It is shown that the present method was successfully applied to a planar manipulator. (© 2015 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim)     

Network design problem with relays: A genetic algorithm with a path-based crossover and a set covering formulation

The network design problem with relays arises in telecommunications and distribution systems where the payload must be reprocessed at intermediate stations called relays on the route from its origin to its destination. In fiber-optic networks, for example, optical signals may be regenerated several times to overcome signal degradation because of attenuation and other factors. Given a network and a set of commodities, the network design problem with relays involves selecting network edges, determining a route for each commodity, and locating relays to minimize the network design cost. This paper presents a new formulation to the problem based on set covering constraints. The new formulation is used to design a genetic algorithm with a specialized crossover/mutation operator which generates a feasible path for each commodity, and the locations of relays on these paths are determined by solving the corresponding set covering problem. Computational experiments show that the proposed approach can outperform other approaches, particularly on large size problems.     

Counting Dyck Paths by Area and Rank

The set of Dyck paths of length 2n inherits a lattice structure from a bijection with the set of noncrossing partitions with the usual partial order. In this paper, we study the joint distribution of two statistics for Dyck paths: area (the area under the path) and rank (the rank in the lattice). While area for Dyck paths has been studied, pairing it with this rank function seems new, and we get an interesting (q, t)-refinement of the Catalan numbers. We present two decompositions of the corresponding generating function: One refines an identity of Carlitz and Riordan; the other refines the notion of γ-nonnegativity, and is based on a decomposition of the lattice of noncrossing partitions due to Simion and Ullman. Further, Biane’s correspondence and a result of Stump allow us to conclude that the joint distribution of area and rank for Dyck paths equals the joint distribution of length and reflection length for the permutations lying below the n-cycle (12· · ·n) in the absolute order on the symmetric group.     

On routing in VLSI design and communication networks

In this paper, we study the global routing problem in VLSI design and the multicast routing problem in communication networks. First we propose new and realistic models for both problems. In the global routing problem in VLSI design, we are given a lattice graph and subsets of the vertex set. The goal is to generate trees spanning these vertices in the subsets to minimize a linear combination of overall wirelength (edge length) and the number of bends of trees with respect to edge capacity constraints. In the multicast routing problem in communication networks, a graph is given to represent the network, together with subsets of the vertex set. We are required to find trees to span the given subsets and the overall edge length is minimized with respect to capacity constraints. Both problems are APX-hard. We present the integer linear programming (LP) formulation of both problems and solve the LP relaxations by the fast approximation algorithms for min-max resource-sharing problems in [K. Jansen, H. Zhang, Approximation algorithms for general packing problems and their application to the multicast congestion problem, Math. Programming, to appear, doi:10.1007/s10107-007-0106-8] (which is a generalization of the approximation algorithm proposed by Grigoriadis and Khachiyan [Coordination complexity of parallel price-directive decomposition, Math. Oper. Res. 2 (1996) 321-340]). For the global routing problem, we investigate the particular property of lattice graphs and propose a combinatorial technique to overcome the hardness due to the bend-dependent vertex cost. Finally, we develop asymptotic approximation algorithms for both problems with ratios depending on the best known approximation ratio for the minimum Steiner tree problem. They are the first known theoretical approximation bound results for the problems of minimizing the total costs (including both the edge and the bend costs) while spanning all given subsets of vertices.     

The use of stochastic analytic center for yield maximization of systems with general distributions of component values

This paper presents a new method for maximizing manufacturing yield when the realizations of system components are dependent random variables with general distributions. The method uses a new concept of stochastic analytic center introduced herein to design the unknown parameters of component values. Design specifications define a feasible region which, in the nonlinear case, is linearized using a first-order approximation. The resulting problem becomes a convex optimization problem. Monte Carlo simulation is used to evaluate the actual yield of the optimal designs of a tutorial example.     

几个著名网络的限长路径

设给出了（h,ψ）-η限长路径问题是图论中的Menger定理的变形和推广，在实时容错网络设计和分析中有重要意义。对于给定的正整数d,Ad(D)表示网络D中任何距离至少为2的两顶点之间内点不交且长度都不超过d的路的最大条数；Bd(D)表示D的顶点子集B中的最小顶点数使得D－B的直径大于d.已证明确定Ad(D)的问题是NPC问题，而且显然有不等式Ad(D)≤Bd(D)。本文考虑D为超立方体网络、De Bruijn网络和Kautz网络，对d的不同值确定了Ad(D)及Bd(D),而且均有Ad(D)=Bd(D)。     

Defects analysis and improvement of a chaotic logic gate

We introduced one chaotic logic gate design and described its performance defects. These defects, namely nondeterminacy and variability of the output signal, were depicted and analysis for the reasons behind them was done. Further more, a new logic gate design by changing the variable under control is proposed. By successfully overcoming defects of the prototype, the new chaotic logic gate can be better applied to a complicated computing architecture.     

A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing

We generalize Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices we label subgraphs which partition the given graph. We can achieve much better running times if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy.As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, our algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with a state-of-the-art routing tool on leading-edge industrial chips.     

The effect of crack faces contact interaction on the critical strain in composites under compressive loading

Aviation and aerospace structural components made of composite laminates due to their internal structure and manufacturing methods often contain a number of inter- and intra-component defects which size, dispersion and interaction alter significantly the critical compression strain level [1]. The current study investigates the effect of the cracks interaction and crack faces contact interaction on the critical strain in laminar transversally isotropic material (cross-ply) compressed in a static manner along interlaminar defects. The frictionless Hertzian contact and the shear and extensional mode of stability loss are considered for the interacting crack faces. The statement of the problem is based on the most accurate approach, the model of piecewise-homogenous medium and the 3-D stability theory [2]. The moment of stability loss in the microstructure of material is treated as the onset of the fracture process. The complex non-classical fracture mechanics problem is solved utilizing the finite elements analysis. The results are obtained for the typical dispositions of cracks. It was found that the crack faces contact interaction alter significantly the critical strain level of the composite. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)     

A further generalisation of the planar cubic Bézier spiral

Spiral segments are useful in the design of fair curves. They are important in CAD/CAM applications, the design of highway and railway routes, trajectories of mobile robots and other similar applications. Cubic Bézier curves are commonly used in curve and surface design because they are of low degree, are easily evaluated, and allow inflection points. This paper generalises earlier results on planar cubic Bézier spiral segments and examines techniques for curve design using the new results.     

Decision Support for the Design of a New Production Plant Using Visual Interactive Simulation

Following promising results in test markets and successful pilot-scale manufacturing, the Board of a major Canadian manufacturer took the decision to proceed to develop the design for a full-scale production plant for a new advanced-technology product. The success of this new product was seen as critical to the Company's future, but Company personnel had limited experience with the new production technology and with the design of plants of this large scale. Finally, competitors from the USA and Europe were known to be working on similar products resulting in a sense of urgency in getting the product to the marketplace. A visual interactive decision support system built around a simulation model was developed using a methodology designed to help management understand the plant design issues and to help them resolve various key plant design options. When completed, the model gave management a tool which was used to analyse alternative plant designs and different production and manpower scheduling scenarios under a broad range of production conditions. The intensity of worldwide competition in this new product market, and the critical importance of this product to this Canadian corporation, have led to the decision to omit the name of the corporation from this article. In addition, certain production details have been disguised.     

Efficient preprocessing for VLSI optimization problems

Advances in technology for the manufacturing of integrated circuits have resulted in extremely large, and time consuming, problems on how to lay out components for optimal circuit performance. These problems can be written as mixed integer programs which are easily relaxed to linear programs with a very high number of variables and constraints. The relaxed programs can often be solved by applying state-of-the-art linear programming software, however these solutions come at the expense of long solution time. In this paper we show that, by considering the structure inherent in VLSI problems, one can specialize classical preprocessing algorithms to take into account the standard form of the constraint matrix for VLSI problems, thereby achieving improved preprocessing results with relatively little effort. We provide analysis showing our preprocessing techniques are accurate and provide some numerical testing demonstrating the increased efficiency. The numerical tests also demonstrate that using our preprocessing in conjunction with internal preprocessing methods that come with many linear program solvers, can improve the overall performance of the linear program solver and its preprocessor.     

A genetic algorithm for cellular manufacturing design and layout

Cellular manufacturing (CM) is an approach that can be used to enhance both flexibility and efficiency in today’s small-to-medium lot production environment. The design of a CM system (CMS) often involves three major decisions: cell formation, group layout, and group schedule. Ideally, these decisions should be addressed simultaneously in order to obtain the best results. However, due to the complexity and NP-complete nature of each decision and the limitations of traditional approaches, most researchers have only addressed these decisions sequentially or independently. In this study, a hierarchical genetic algorithm is developed to simultaneously form manufacturing cells and determine the group layout of a CMS. The intrinsic features of our proposed algorithm include a hierarchical chromosome structure to encode two important cell design decisions, a new selection scheme to dynamically consider two correlated fitness functions, and a group mutation operator to increase the probability of mutation. From the computational analyses, these proposed structure and operators are found to be effective in improving solution quality as well as accelerating convergence.     

Microstructure evolution during rolling and annealing of mild steels

The process chain for components made of sheet metals consists of different forming techniques like hot rolling, cold rolling, and deep drawing as well as heat treatment operations like annealing. For the design and optimization of the whole manufacturing process and the final component behavior, a correct representation of the material behavior and the application of appropriate numerical simulation techniques are required. For our first investigations, a ferritic mild steel DC04, which is a typical steel grade for automotive applications, is analyzed. Therefore, specimens are taken out of a real manufacturing process after hot and cold rolling and after annealing. These specimens are intensively investigated in order to study the texture evolution and the development of other material properties, like yield function during the process chain. In this paper different homogenization methods are used to simulate the texture evolution during cold rolling. The results are compared concerning accuracy and efficiency of the considered models. (© 2010 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim)     

超大规模集成电路布局的优化模型与算法

布局确定集成电路单元在芯片中的具体位置,在单元互不重叠的基础上优化一些性能指标。该问题是NP困难的组合优化问题,是超大规模集成电路物理设计的核心问题之一,对集成电路的性能指标,如线网可布通性、时延、功耗、电路可靠性等有重大影响。在现代的集成电路设计中,布局问题通常包含数百万个集成电路单元,以及大小相异的异质性模块,和各种复杂的布局约束。目前的超大规模集成电路布局算法通常分解为总体布局、布局合法化和详细布局三个步骤。根据近年来集成电路布局算法的研究进展,综述并分析集成电路的总体布局、布局合法化和详细布局的相关优化模型和算法,并展望进一步的研究方向。