High frequency performance of Si/sub 1-x/Ge/sub x//Si/sub 1-y/Ge/sub y//Si/sub 1-x/Ge/sub x/ HBTs

The results of a theoretical study of the performance of high speed SiGe HBTs is presented. The study includes a group of SiGe HBTs in which the Ge concentration in the base is 20% higher than that in the emitter and collector (i.e. y=x+0.2). It is shown that the composition dependences of f/sub T/ and the F/sub max/ are non-monotonic. As the Ge composition in the emitter and collector layers is increased, f/sub T/ and f/sub max/ first decrease, then remain constant and finally increase to attain their highest values.<>     

A super self-aligned selectively grown SiGe base (SSSB) bipolartransistor fabricated by cold-wall type UHV/CVD technology

A novel selective epitaxial growth (SEG) technology for fabricating the intrinsic SiGe-base layer of a double poly-Si self-aligned bipolar transistor has been developed. Selectively grown Si and SiGe-alloy layers were obtained by using Si₂H₆+GeH₄+Cl₂+B₂ H₆ gas system using cold-wall ultra-high vacuum (UHV)/CVD. We have optimized the growth conditions so that Si or SiGe grows selectively against Si₃N₄ both on single crystalline Si and on poly-Si of a structure consisting of a poly-Si layer overhanging the single crystalline Si substrate. The selective growth is maintained until the growth from the bottom Si and the top poly-Si coalesce. This selective growth permits a novel emitter-base self-aligned transistor which we call a super self-aligned selectively grown SiGe base (SSSB) HBT     

Noise performance of Si/Si/sub 1-x/Ge/sub x/ FETs

Noise characteristics are evaluated for SiGe/Si based n-channel MODFETs and p-channel MOSFETs. The analysis is based on a self-consistent solution of Schrodinger and Poisson's equations. The model predicts a superior minimum noise figure for an n-channel MODFET at 77 K. P-channel MOSFETs behave similar to n-channel devices operating at 300 K. Minimum noise figure decreases with increasing quantum well (QW) width for both n- and p-channel devices. However, the p-channel devices are less sensitive to QW width variation. Minimum noise temperature behaves similarly. As observed, a range of doped epilayer thickness exists where minimum noise figure is a minimum for both n- and p-channel FETs.<>     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

Comparison of GexSi1—x Grown by UHV／CVD from Si2H6／GeH4 and SiH4／GeH4

Using double crystal X-rays diffraction (DCXRD) and atomic force microscopy (AFM), the results of Ge x Si 1- x grown by UHV/CVD from Si 2H 6 and SiH 4 are analyzed and compared. Adsorbates can migrate to the energy-favoring position due to the slow growth rate from SiH 4. In this case, a Si buffer that isolates the effect of substrate on epilayer could not be grown, which results in a pit penetrating into epilayer and buffer. The FWHM is 0.055° in DCXRD from SiH 4. The presence of diffraction fringes is an indication of an excellent crystalline quality. The roughness of the surface is improved if grown by Si 2H 6; however, the crystal quality of the Ge x Si 1- x material became worse than that from SiH 4 due to much larger growth rate from Si 2H 6. The content of Ge is obtained from DCXRD, which indicates the growth rate from Si 2H 6 is largest, then GeH 4, and that from SiH 4 is least.     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

Properties of Si/sub 3/N/sub 4//Si/sub x/Ge/sub 1-x/ metal-insulator-semiconductor capacitors

The density of fast interface states was studied in Si/sub 3/N/sub 4//Si/sub 0.8/Ge/sub 0.2/ metal-insulator-semiconductor (MIS) capacitors. The interface state density does not appear to be strongly affected by the presence of a thin Si interlayer between the nitride and SiGe alloy. This is in contrast to the results when SiO/sub 2/ is used as the insulator material in similar structures.<>     

Waveguided electro-optical intensity modulation in a Si/Ge/sub x/Si/sub 1-x//Si heterojunction bipolar transistor

Optical phase-and-amplitude modulation at 1.55 mu m in an electro-optic guided-wave Si/Ge/sub 0.2/Si/sub 0.8//Si HBT is investigated using computer-aided modelling and simulation. At an injection of 10/sup 19/ electrons per cm/sup 3/, an intensity modulation of 10 dB is predicted for an active length of 390 mu m.<>     

High-performance, metamorphic In/sub x/Ga/sub 1-x/As tunnel diodes grown by molecular beam epitaxy

Thin In/sub x/Ga/sub 1-x/As tunnel junction diodes having compositions from x=0.53 to 0.75 that span a range of bandgap energies from 0.74 to 0.55 eV, were grown on InP and metamorphic, step-graded In/sub x/Al/sub 1-x/As/InP substrates using molecular beam epitaxy and evaluated in the context of thermophotovoltaic (TPV) applications. Both carbon and beryllium were investigated as acceptor dopants. Metamorphic tunnel diodes with a bandgap of 0.60 eV (x=0.69) using carbon acceptor doping displayed highest peak current densities, in excess of 5900 A/cm/sup 2/ at a peak voltage of 0.31 V, within a 200 /spl Aring/ total thickness tunnel junction. Identically doped lattice-matched tunnel diodes with a bandgap of 0.74 eV exhibited lower peak current densities of approximately 2200 A/cm/sup 2/ at a higher peak voltage of 0.36 V, consistent with the theoretical bandgap dependence expected for ideal tunnel diodes. Specific resistivities of the 0.60 eV bandgap devices were in the mid-10/sup -5/ /spl Omega/-cm/sup 2/ range. Together with their 200 /spl Aring/ total thickness, the electrical results make these tunnel junctions promising for TPV applications where low-resistance, thin metamorphic tunnel junctions are desired.     

Investigations of high-performance GaAs solar cells grown on Ge-Si/sub 1-x/Ge/sub x/-Si substrates

High-performance p/sup +//n GaAs solar cells were grown and processed on compositionally graded Ge-Si/sub 1-x/Ge/sub x/-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm/sup 2/ solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm/sup 2/ did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

Effect on ion implanted germanium profile on the characteristics of Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors

An optimum profile for Ge ion implantation in SiGe/Si heterojunction bipolar transistors is determined by using a two-dimensional simulator code for advanced semiconductor devices. The simulation code is based on a two-dimensional drift-diffusion model for heterostructure degenerate semiconductors with nonparabolicity included in the energy band structure. The model allows accurate simulations of carrier transport in short base devices. The simulation results indicate that for high current gain the Ge profile maximum must be close to the base-collector junction, and that the unavoidable tail of the implanted germanium in the collector region does not deteriorate the gain.<>     

UV/UHV/CVD生长应变Si1-xGex层

应用紫外光化学气相淀积技术在450和480℃超高真空的背景下在Si衬底上分别生长出应变Si1-xGx和Si材料.在此低温下,有效地控制了衬底中的杂质外扩以及界面的不清晰.X射线分析结果表明Si1-xGex材料结晶状况良好,二次离子质谱分析结果表明多层Si1-xGex/Si材料界面陡峭,说明该技术能够生长出高质量的应变Si1-x-Gex/Si材料.     

Growth of Strained Si1－xGex Layer by UV/UHV/CVD

Strained Si1－xGex and Si materials are successfully grown on Si substrate by ultraviolet light chemical vapor deposition under ultrahigh vacuum at a low substrate temperature of 450℃ and 480℃，respectively.At such low temperature,autodoping effects from the substrate and interdiffusion effects at each interface could be suppressed efficiently.The strained Si1－xGex and multilayer Si1－xGex /Si structures are examined by X-ray diffraction,SMIS,etc.,and it is found that the materials have good crystallinity and the rising and falling edges are steep.The technique has a capability of growing highquality Si1－xGex /Si strained layers.     

Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si/sub 1-y/C/sub y/ incorporation

We have demonstrated the fabrication of n/sup +/-p gated diodes using low-temperature annealing of 700/spl deg/C for 30 s with a significantly reduced junction leakage current. This is achieved with the incorporation of an epitaxially grown Si/sub 1-y/C/sub y/(y=0.0007) layer in the substrate located at the end-of-range (EOR) of arsenic implantations. The carbon devices show effectively suppressed EOR defects in the cross-sectional transmission electron microscopy images and leakage characteristics similar to the controlled silicon device fabricated under high-temperature annealing of 950/spl deg/C for 30 s. Arrhenius measurement of the leakage profiles has indicated identical leakage mechanism for both the pure silicon and carbon devices, thus signifying the substantial elimination of the secondary EOR defects resulted from the implantations despite the low-temperature annealing of the latter.     

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si/sub 1-x/Ge/sub x/ S/D) technology. Experimental results on Si/sub 1-x/Ge/sub x/ S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si/sub 1-x/Ge/sub x/ is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si/sub 1-x/Ge/sub x/ and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si/sub 1-x/Ge/sub x/ S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes.     

MOS capacitors on epitaxial Ge-Si/sub 1-x/Ge/sub x/ with high-/spl kappa/ dielectrics using RPCVD

We report the successful growth of MOS capacitor stacks with low temperature strained epitaxial Ge or Si/sub 1-x/Ge/sub x/(x=0.9) layer directly on Si substrates, and with HfO/sub 2/(EOT=9.7 /spl Aring/) as high-/spl kappa/ dielectrics, both using a novel remote plasma-assisted chemical vapor deposition technique. These novel MOS capacitors, which were fabricated entirely at or below 400/spl deg/C, exhibit normal capacitance-voltage and current-voltage characteristics.     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

A novel dynamic threshold Voltage MOSFET (DTMOS) using heterostructure channel of Si/sub 1-y/C/sub y/ interlayer

We have demonstrated the fabrication of dynamic threshold voltage MOSFET (DTMOS) using the Si/sub 1-y/C/sub y/(y=0.005) incorporation interlayer channel. Compare to conventional Si-DTMOS, the introduction of the Si/sub 1-y/C/sub y/ interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. This novel Si/sub 1-y/C/sub y/ channel heterostructure MOSFET exhibits higher transconductance and turn on current.