On the pseudo-subthreshold characteristics ofpolycrystalline-silicon thin-film transistors with large grain size

A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator     

A strategy for modeling of variations due to grain size inpolycrystalline thin-film transistors

A strategy is presented for modeling of performance variation in polycrystalline thin-film transistors (TFT's) due to grain size variation. A Poisson area scatter is used to model the number of grains in a TFT, which is converted to grain size and substituted into physically based models for threshold and mobility. An increase in device variation is predicted as the device and grain sizes converge through scaling or process changes. Comparison of the model with measurements of NMOS TFT's results in reasonable agreement     

Direct writing of inkjet-printed short channel organic thin film transistors

A direct-writing fabrication process for fully inkjet-printed short-channel organic thin-film transistors (OTFTs) has been developed. Channels as narrow as 800 nm between two printed Ag electrodes were achieved by printing a special Ag ink on an SU-8 interlayer, which can be partially dissolved by the solvents used in the Ag ink. The ridge formed along the printed Ag line edges due to redistribution of the interlayer material during the drying process limits the ink spread, and separates neighboring printed lines, and is the key to defining an ultra-narrow channel for transistor fabrication. The short-channel OTFTs fabricated using this technique have demonstrated well-defined linear and saturation regimes. An extracted mobility of 0.27 cm²/Vs with an on/off ratio of 10⁵ was obtained at a driving voltage of −12 V. The excellent performance of these devices demonstrates the potential of this technique in fabrication of short-channel devices using standard printing technologies.     

Fabrication of vertical channel top contact organic thin film transistors

Vertical channel top contact (TC) organic thin film transistors (OTFTs) have been successfully realized on Si substrates with SiO₂ as gate insulators and P3HT(poly ∼3-hexylthiophene) as organic semiconductors. The active channel region was defined by a steep step through a Si etching method. Source and drain metal contacts were deposited by vacuum evaporation through a shadow mask at a high tilting angle. Top contact transistors with channel lengths 5 μm can be fabricated with a relatively simple and efficient (yield >85%) fabrication process with only two photolithography steps (two photo masks) while no need for high-resolution and precision alignment for channel definition. Measurement results showed that the vertical channel BC (bottom contact) devices have compatible performance with planar BC devices. However, vertical channel TC transistors showed improved performance with double field effect mobilities and three times larger current ON/OFF ratios than vertical channel BC devices.     

Unusually abrupt switching in submicrometer thin-film transistorsusing a polysilicon film with enhanced grain size

Unusually abrupt drain current change observed in polysilicon thin-film transistors (TFTs) with a channel length and width of 1 μm or smaller is discussed. The polysilicon used to fabricate the devices was deposited by low-pressure chemical vapor deposition (LPCVD) and the grain size of the film was enhanced by silicon ion implantation followed by a low-temperature anneal. The TFTs exhibited an abrupt drain current change of more than five orders of magnitude for a corresponding gate voltage change of less than 40 mV. A self-limiting positive feedback loop due to impact ionization currents and/or a parasitic bipolar effect are suggested as possible explanations     

Performance of thin-film transistors with ultrathin Ni-MILCpolycrystalline silicon channel layers

High-performance, low-temperature processed thin-film transistors (TFTs) with ultrathin (30-nm) metal induced laterally crystallized (MILC) channel layers were fabricated and characterized. Compared with the MILC TFTs with thicker (100 nm) channel layers, the ones with the 30-nm channel layers exhibit lower threshold voltage, steeper subthreshold slope, and higher transconductance. Furthermore, the comparatively lower off-state leakage current and the higher on-state current of the “thin” devices also imply a higher on/off ratio. At a drain voltage of 5 V, an on/off ratio of about 3×10 ⁷ was obtained for the 30-nm TFTs, which is about 100 times better than that of the 100-nm TFT's. No deliberate hydrogenation was performed on these devices     

Quantum size impacts on the threshold voltage in nanocrystalline silicon thin film transistors

Based on the analysis of Poisson equation, an analytical threshold voltage model including quantum size effect of nc-TFTs (nanocrystalline silicon thin film transistor) has been proposed in this paper. The results demonstrate that the proposed simplified expression of threshold voltage agree perfectly with numerical calculation. The threshold voltage in nc-TFTs strongly depends on the size of silicon grain when the size of silicon grain is less than 20 nm. Such a strong dependent relation results from the large changes in the bandgap and dielectric constant due to quantum size effects when the size of silicon grain is in the regime of nano-scale. The theoretical investigation also demonstrates that the grain boundary trap density compared to the active dopant density gives a main contribution to the threshold voltage. This implies that the grain size must be larger than 30 nm in order to avoid threshold voltage variation from different technological processes.     

Investigation of grain boundary control in the drain junction on laser-crystalized poly-Si thin film transistors

This letter investigates the influences of grain boundaries in the drain junction on the performance and reliability of laser-crystalized poly-Si thin film transistors (TFTs). A unique test structure where the channel region includes 150-nm-thick laser-crystalized poly-Si with small grain sizes and a 100-nm-thick one with large grain sizes is fabricated. Different behaviors in the electrical characteristics and reliability of a single TFT are observed, first under measurements of the forward mode and then under measurements of the reverse mode. This is due to the different number of grain boundaries in the drain junction. Grain boundaries in the drain junction were found to cause reduced ON/OFF current ratio, variations in threshold voltage with drain bias, significantly increased kink effect in the output characteristics, and poor hot-carrier stress endurance.     

Preparation of thin-film transistors with chemical bath depositedCdSe and CdS thin films

The authors have fabricated the thin-film transistor (TFT) with CdSe and CdS semiconductor thin films, prepared by a low temperature chemical bath deposition (CBD) method, as an active layer. The ON-current values of the CdSe-TFTs and CdS-TFTs at a gate bias of 10 V and a source-drain voltage of 10 V are about 100 μA and 5 μA, respectively. The OFF-current values of the CdSe-TFTs and CdS-TFTs at the source-drain voltage of 10 V are less than 10 pA. The fabricated CdSe-TFTs exhibited a field effect mobility of 15 cm²/V-s, threshold voltage of 3.5 V, subthreshold slope of 0.5 V/dec., and ON/OFF current ratios exceed 10⁷. A field effect mobility of I cm ²/V-s, a threshold voltage of 2.6 V, a subthreshold slope of 0.6 V/dec., and an ON/OFF current ratios exceed 10⁶ were observed for CdS TFTs     

Dependence of off-leakage current on channel film quality in poly-Si thin-film transistors and analysis using device simulation

The dependence of off-leakage current on channel film quality in poly-Si thin-film transistors has been analyzed using two-dimensional device simulation. It is found that the off-leakage current decreases as the intragrain trap density decreases for the low V_gs. This is because the Phonon-assisted tunneling with Poole-Frenkel effect is the dominant mechanism of the carrier generation and the generation rate of carrier pair decreases as the intragrain trap density decreases. On the other hand, the off-leakage current slightly increases as the intragrain trap density decreases for the high V_gs. This is because the band-to-band tunneling is the dominant mechanism and the influence of the intragrain trap density to the carrier conductance is larger than that to the generation rate.     

Influence of channel layer and passivation layer on the stability of amorphous InGaZnO thin film transistors

The electrical stability of amorphous InGaZnO (a-IGZO) TFTs with three different channel layers was investigated. Compared with the single channel layer, the a-IGZO TFT with double stacked channel layer showed the lowest threshold voltage shift with slightly change in field effect mobility and sub-threshold swing under positive and negative gate bias stress tests. Moreover, sputtered SiN_x thin film was served as passivation layer where the V_th shift in bias stress effect evidently became less. It was found that the passivated a-IGZO TFT with double stacked channel layer still exhibited the best stability. The results prove that the stability of a-IGZO TFTs can be effectively improved by using double stacked channel layer and passivation layer.     

The effects of grain boundaries in the electrical characteristics of large grain polycrystalline thin-film transistors

High-performance low-voltage thin-film transistors (TFTs) can be fabricated by grain-enhancement methods such as nickel-seeded metal-induced lateral crystallization (MILC). Electrical characteristics of the TFTs may vary due to the existence of the grain boundaries in the device active region. To obtain the best device characteristics, the effect of grain boundaries on the device must be investigated. In this paper, the cumulative distributions of the device properties such as leakage current, threshold voltage, subthreshold slope, and field-effect mobility as a function of different channel lengths and widths were studied. In general, the grain boundary effects decrease with device size. Devices with short channel lengths and wide channel widths may suffer from degradation due to large leakage current. Moreover, the effects due to the location of the nickel-seeding region on device characteristics were investigated. These include the effect of the longitudinal and lateral grain boundaries and the distance between the nickel seeding region and the device. Finally, a design guideline to reduce the grain boundary effect is presented.     

Characterization of organic thin film transistors with hysteresis and contact effects

We propose two procedures to extract information about the trapping processes that occur in organic thin film transistors (OTFTs) that exhibit both contact and hysteresis effects. In particular, the variation of trapped charge during hysteresis cycles is determined by the separate analysis of current–voltage curves for the intrinsic transistor and for the contact region. The extraction of these curves is done with the help of our previous compact model that reproduces the current–voltage characteristics of OTFTs with contact effects. The model is used to fit experimental output characteristics with hysteresis and to extract the parameters of the model, such as the mobility and the threshold voltage. The variation of the threshold voltage with trapped charges during voltage cycling and using existing transistor models results in different sets of parameters needed to reproduce the experimental data. However, not all these parameters have proper physical meanings. In order to find a unique physical solution, the current–voltage curves of the contacts and current–voltage curves of the intrinsic transistor, extracted from the output characteristics measured at the transistor terminals, are separately analyzed. The study of the evolution with the gate voltage of the free-charge density in the contact allows for finding this unique solution. The results of this method are compared with published results that use more elaborate experimental techniques, such as the four-terminal method or transient experiments.     

表面修饰的ZnPc薄膜晶体管性能研究

以热生长的SiO2作为栅绝缘层,酞菁锌(ZnPc)作为有源层,研究了具有十八烷基三氯硅烷(OTS,C18H37SiCl3)/SiO2双绝缘层结构的有机薄膜晶体管(OTFT)。实验表明,采用OTS可以有效地降低SiO2栅绝缘层的表面能并改善表面的平整度,器件的场效应迁移率提高了3.5倍,漏电流从10-9A降到10-10A,阈值电压降低了5 V,开关电流比从103增加到104。结果显示,具有OTS/SiO2双绝缘层的器件结构能有效改进OTFT的性能。     

Improving the performance of the organic thin-film transistors with thin insulating lithium fluoride buffer layer

The pentacene-based organic thin-film transistors (OTFTs) with a thin insulating lithium fluoride (LiF) buffer layer between the pentacene and source/drain electrodes were fabricated. Compared with conventional OTFTs, the introduction of the buffer layer (1 nm) leads to field-effect mobility increases from 0.16 to 0.5 cm²/Vs, and threshold voltage downshifts from −19 to −8 V for the linear region. The on/off current ratio is improved to a level of 10⁵ for the off-state current decreasing. These improvements are attributed to (i) tunneling injection through the LiF layer and (ii) interface dipole energy barrier decreasing and contact resistance reduction between pentacene and Au. The results demonstrate that it is an effective method to improve the device characteristics by using a buffer layer.     

Organic thin film transistors with asymmetrically placed source and drain contact

This work describes the impact of different source/drain contact arrangements on organic thin film transistor’s speed characterized by unity gain frequency. 2D numerical simulations are used to analyze four different device structures resulting from placement of either of the contacts at the bottom or on top of organic semiconductor film. It is shown that variations in contact placement result in differences in device speed due to differences in transconductance and gate–drain capacitances. An asymmetrical device structure with source at the bottom and drain at the top is found to yield the highest unity gain frequency at a carefully chosen semiconductor film thickness.     

Electrical evaluation of thin film CdS diodes and transistors

Thin film active devices are of current interest to semiconductor electronics, since their integration with passive thin film components will eventually lead to a new concept in circuitry for microelectronics. This paper reports on electrical performances of thin film active devices fabricated entirely by vacuum vapor deposition techniques. CdS is used for the semi-insulating material. Thin film diodes show space-charge-limited current properties which are modified by the presence of traps. Experimental data on thin film transistors are in good agreement with theory for the insulated-gate field effect transistor. The theory predicts current-voltage and gain-bandwidth capability of the device.     

基于PSSNa的平面侧栅型氧化物双电层薄膜晶体管

双电层薄膜晶体管(EDLTs)凭借其低电压、多栅调控以及对神经突触的模拟而备受关注.为了实现一种基于聚电解质的新型平面侧栅结构的EDLTs,采用磁控溅射制备的氧化铟镓锌(IGZO)沟道和氧化铟锌(IZO)电极,试验了三种不同的聚电解质作为栅介质.发现聚苯乙烯磺酸钠(PSSNa)可以作为栅介质材料实现器件的良好工作.由于...     

Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage

A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved.