Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

In the present study, a technology for the formation of a submicron GaAs MESFET gate of 0.5–0.1 μm in length and above 0.5 μm in height using a four-layer dielectric dummy gate was developed. Techniques of chemical and plasma-chemical deposition from a gaseous phase, differing in etch rates in a buffer solution of hydrofluoric acid, were used to prepare silicon oxide films. Different constructions of a multilayer structure with varying sequences of layers and thicknesses were studied. The conditions of chemical and plasma-chemical etching of dielectrics allowing a dummy double-T-gate to be formed were determined. The employment of a sophisticatedly shaped dummy gate made it possible to obtain a gate electrode of a large cross section with a low length. The possibility in principle to fabricate a MESFET gate with a length of up to Lg = 0.1 μm using lithographic procedures with a minimal resolution of 1.0 μm was demonstrated.     

DPN MOS绝缘栅氮处理技术

分析了90nm及其以上技术、栅氧化及其氮处理工艺的局限性,强调了等离子体氮处理技术在90nm及其以下技术中的必要性.介绍了应用材料公司DPN MOS绝缘栅氮处理技术,并出示了部分试验数据.     

Effects of the sputtering deposition process of metal gate electrode on the gate dielectric characteristics

Effects of the N₂-introduced reactive sputtering deposition of metal gate electrodes on the gate leakage current and the dielectric reliability of the W/WN_x and W/TiN metal gate MOS capacitors are investigated. The gate dielectric characteristics of W gate MOS capacitor are degraded during the sputtering deposition of the gate electrode. However, the sputtering process-induced degradation of the dielectric characteristics is improved by increasing N₂ flow ratio during the deposition of WN_x gate electrode. This improvement is considered to be due to the termination of the dangling bonds in the surface-damaged layer in the gate dielectric by the surface nitridation. The nitridation of 1.5 at.% is found to effectively improve both gate leakage characteristics and dielectric reliability of the W/WN_x gate MOS capacitor to a level comparable to those of the poly-Si gate. The characteristics of W/WN_x gate MOS transistors are also improved by the surface nitridation through the decrease of the gate leakage current. However, the surface nitridation enhances the electron trapping probability under substrate injection, which results in the lower activation energy of CVS–Q_bd of metal gate MOS capacitors.     

GaAs MOSFET using InAlP native oxide as gate dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.     

Carrier mobility in MOSFETs fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrode, and self-aligned source and drain

A study of electron and hole mobilities for MOSFET devices fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrodes and self-aligned source and drain is presented. High effective electron and hole mobilities, 250 cm/sup 2//V/spl middot/s and 70 cm/sup 2//V/spl middot/s, respectively, were measured at high effective field (>0.5 MV/cm). The NMOSFETs have an equivalent oxide thickness (EOT) of 1.3 nm and the PMOSFETs have an EOT of 1.5 nm. The effect of interface engineering on the electron and hole mobilities is discussed.     

Valence band structure of rubrene single crystals in contact with an organic gate dielectric

Organic field effect transistors (OFETs) using crystalline organic semiconductors are of great interest because of their well-defined structural and electronic properties to study the intrinsic charge carrier transport mechanisms in π-conjugated molecular solids, as well as to unravel their potential to be applied as a novel type of electronic device. In the present study, the valence band structure of the channel region of an OFET is proposed based on photoemission results of a well-defined interface between a dielectric molecular monolayer and single crystals of 5,6,11,12-tetraphenyltetracene (rubrene) which is known to exhibit the highest field effect mobility of all organic semiconductors at room temperature. Commensurate growth of clusters of tetratetracontane (TTC; n-C₄₄H₉₀) on the rubrene single crystal surface and their morphological transformation into a uniform overlayer were observed by atomic force microscopy. Photoelectron spectroscopy measurements at various electron take-off angles were then conducted to derive the valance band width of the rubrene single crystal covered by the TTC overlayers. The valence band width at this hetero-interface was found to be equivalent to that of the pristine rubrene, which suggests an unchanged ‘band effective mass ?²(d²E/dk_||²)’ of accumulated holes even at the vicinity of hydrocarbon-based gate dielectrics.     

A new MoSi2/Thin poly-Si gate process technology without dielectric degradation of a gate oxide

The dielectric degradation phenomena in gate oxides of MoSi²/thin n⁺poly-Si (<100 nm) gate structure which appeared after high-temperature annealing have been analyzed in detail. Analyses included obtaining the correlation between gate oxide dielectric characteristics and various factors like phosphorus concentration in poly-Si, native oxide on poly-Si, sheet resistance of MoSi², and the SEM or TEM observations of textures of MoSi², poly-Si, and gate oxide. From analyses, it was concluded that the local reaction of molybdenum silicide with poly-Si under the presence of a barrier, like the thick native oxide on poly-Si formed before MoSi²deposition, results in the damage to a gate oxide through a thin poly-Si layer during annealing. Based upon analytical results, a new MoSi²/thin poly-Si gate process without dielectric degradation has been developed, in which the direct MoSi²deposition on undoped poly-Si to suppress the native oxide growth and phosphorus implantation into MoSi²were introduced. The process provided a good dielectric strength of a gate oxide even to the device with a poly-Si layer as thin as 50 nm, an easy dry etching without undercutting of poly-Si, and stable device characteristics and reliabilities compatible to a conventional poly-Si gate process.     

Gentle FUSI NiSi metal gate process for high-k dielectric screening

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).     

Pt-Germanide Schottky source/drain Germanium p-MOSFET with HfO/sub 2/ gate dielectric and TaN gate electrode

Schottky source/drain (S/D) transistors using Pt-germanide and HfO/sub 2//TaN gate stack are fabricated on Ge-substrate with conventional self-aligned top-gate process. It was found that Pt-germanide provides promising properties for p-MOSFET: negative effective hole barrier height, low resistivity, atomically sharp junction with Ge with good morphology. Pt-germanide Ge-p-MOSFETs showed well-behaved I/sub D/-V/sub D/ characteristics and much suppressed I/sub off/ compared to Ni-germanide and conventional heavily doped S/D MOSFETs.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.     

Conduction mechanisms in MOS gate dielectric films

This paper reviews the conduction mechanisms in the gate dielectric films of MOSFETs for VLSI and ULSI technologies. They include Fowler–Nordheim tunneling, internal Schottky (or Pool–Frenkel) effect, two-step (or trap-assisted) tunneling, shallow-trap-assisted tunneling, and band-to-band tunneling. The current transport in the gate dielectric films is manly controlled by film material composition, film processing conditions, film thickness, trap energy level and trap density in the films. In general, for a given gate dielectric film, the current transport behaviors are normally governed by one or two conduction mechanisms.     

An X-band dielectric resonator antenna using a single elliptical shaped dielectric resonator

This paper presents design evolution of a single elliptical dielectric resonator antenna to achieve wide measured impedance band-width extending from 8.26 GHz to 12.15 GHz. Design evolved from a right circular cylindrical DRA by varying the dimension along the semi-minor axis and thereby resulting in an elliptical DRA that supports near similar field distribution over the X-band. This similar field variation is achieved by tuning the eccentricity of the elliptical geometry, the feed position as well as height of the DRA. A fabricated prototype is developed and measured results agree well with that obtained from simulation. Apart from wide impedance bandwidth, the observed pattern bandwidth is also similar.     

Defects in silicon oxynitride gate dielectric films

As the aggressive scaling of the metal-oxide-semiconductor structure continues, new reliability challenges in gate dielectric materials now came across as the gate dielectric thickness will be further down scaled to its technological constraint (<3 nm). Since the interface thickness and the capture cross-section of dielectric traps are not scalable, the nano device structures and the giga-scale circuit architectures call for a fabrication process with ultra-high uniformity and repeatability for devices. These put strengthen constraints on the trap density and chemical composition fluctuations of the gate dielectric materials. This paper reviews several important issues of the dielectric traps in oxynitride. Particularly, the paramagnetic defects (Si^•, Si---O---O^•, Si₂N^•), diamagnetic defects (Si---Si, =N---H), dicoordinated Si center (=Si:) and neutral defects (SiO^•, SiOH, Si---O---O---Si) are discussed in detail based on both the experimental and simulation results.     

Fully-depleted SOI devices with TaSiN gate, HfO/sub 2/ gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.     

一种利用门电路实现可靠启动的基准电流源

为了解决电流和模式的基准电路的潜在启动失败问题以及使电路更加低功耗、低复杂度、高稳定性,提出了一种利用数字门电路实现可靠启动的CMOS带隙基准电流源。Spectre仿真表明,在1.8 V电源电压下,功耗为180μW,电路输出20μA参考电流,温度系数为11.9 ppm,线性度为1 054 ppm/V,输出噪声电压为0.1 mV,电源抑制比为-42 dB。采用TSMC0.18μm CMOS工艺流片。测试结果表明,电路能在15.4μs内实现可靠启动,输出参考电压稳定在1.28 V,其温度系数为89 ppm。该基准电流源已经成功地应用于工业自动化无线传感网(WIA)节点芯片的频率综合器中,并取得良好的应用效果。     

The effect of substrate surface roughness on GaN growth using MOCVD process

Efficiency and lifetime of light emitting diodes and laser diodes inversely depend on defect density of the crystal, and reduction of defect density is accomplished by a proper choice of substrate or a deliberate modification of the substrate surface. Buffer growth or nitridation can yield an atomically flat surface and the roughness of a substrate surface for GaN deposition can be controlled by either method such that lateral film growth can be promoted. The effect of nanoscale surface roughness on photoluminescence and crystal quality of GaN/Al₂O₃ (0001) has been studied. The optimal conditions for N₂-nitridation or/and GaN-buffer growth correlate well with the minimum surface roughness and surface morphology as determined by atomic force microscopy and it is suggested that this can be used for process optimization of GaN film growth.     

Flexible metal-insulator-metal capacitor using plasma enhanced binary hafnium-zirconium-oxide as gate dielectric layer

We have used a sol-gel spin-coating process to fabricate a new metal-insulator-metal capacitor comprising 10-nm thick binary hafnium-zirconium-oxide (Hf_xZr_1−xO₂) film on a flexible polyimide (PI) substrate. The surface morphology of this Hf_xZr_1−xO₂ film was investigated using atomic force microscopy and scanning electron microscopy, which confirmed that continuous and crack-free film growth had occurred on the PI. After oxygen plasma pre-treatment and subsequent annealing at 250 °C, the film on the PI substrate exhibited a low leakage current density of 3.22 × 10⁻⁸ A/cm² at −10 V and maximum capacitance densities of 10.36 fF/μm² at 10 kHz and 9.42 fF/μm² at 1 MHz. The as-deposited sol-gel film was oxidized when employing oxygen plasma at a relatively low temperature (∼250 °C), thereby enhancing the electrical performance.     

Direct tunneling gate leakage current in transistors with ultrathinsilicon nitride gate dielectric

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si₃N₄) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms mere extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si ₃N₄ gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.