Low-voltage antimony-doped SnO2 nanowire transparent transistors gated by microporous SiO2-based proton conductors

A battery drivable low-voltage transparent lightly antimony（Sb）-doped SnO2 nanowire electric-double-layer （EDL） field-effect transistor （FET） is fabricated on an ITO glass substrate at room temperature. An ultralow operation voltage of 1 V is obtained on account of an untralarge specific gate capacitance （- 2.14 μF/cm2） directly bound up with mobile ions-induced EDL （sandwiched between the top and bottom electrodes） effect. The transparent FET shows excellent electric characteristics with a field-effect mobility of 54.43 cm2/V. s, current on/off ration of 2 × 104, and subthreshold gate voltage swing （S = dVgs/d（logIds）） of 140 mV/decade. The threshold voltage Yth （0.1 V） is estimated which indicates that the SnO2 namowire transistor operates in an n-type enhanced mode. Such a low-voltage transparent nanowire transistor gated by a microporous SiO2-based solid electrolyte is very promising for battery-powered portable nanoscale sensors.     

The influence of interfacial barrier engineering on the resistance switching of In₂O₃:SnO₂/TiO₂/In₂O₃:SnO₂ device

The I–V characteristics of In2O3:SnO2/TiO2/In2O3:SnO2 junctions with different interfacial barriers are inves- tigated by comparing experiments. A two-step resistance switching process is found for samples with two interfacial barriers produced by specific thermal treatment on the interfaces. The nonsynchronous occurrence of conducting filament formation through the oxide bulk and the reduction in the interfacial barrier due to the migration of oxygen vacancies under the electric field is supposed to explain the two-step resistive switching process. The unique switching properties of the device, based on interfacial barrier engineering, could be exploited for novel applications in nonvolatile memory devices.     

Performance of La₂O₃/InAlN/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La2O3/InAlN/GaN metal-oxide-semiconductor high electron mobility transistors(MOSHEMTs) and InAlN/GaN high electron mobility transistors(HEMTs).The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device,while the gate leakage current in the reverse direction could be reduced by four orders of magnitude.Compared with the HEMT device of a similar geometry,MOSHEMT presents a large gate voltage swing and negligible current collapse.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO₂ /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson’s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson’s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

氧对IZO低压无结薄膜晶体管稳定性的影响

本文在室温下制备了无结结构的低压氧化铟锌薄膜晶体管, 并研究了氧分压对其稳定性的影响. 氧化铟锌无结薄膜晶体管具有迁移率高、结构新颖等优点, 然而氧化物沟道层易受氧、水分子等影响, 造成稳定性下降. 在室温下, 本文通过改变高纯氧流量制备氧化铟锌透明导电薄膜作为沟道层、源漏电极, 分析了氧压对于氧化物无结薄膜晶体管稳定性的影响. 为使晶体管在低电压(<2 V)下工作, 达到低压驱动效果, 本文采用具有双电层效应和栅电容大的二氧化硅纳米颗粒膜作为栅介质; 通过电学性能测试, 制备的晶体管工作电压仅为1 V、 开关电流比大于10⁶、亚阈值斜率小于100 mV/decade以及场效 应迁移率大于20 cm²/V·s. 实验研究表明, 通氧制备的氧化铟锌薄膜的电阻率会上升, 导致晶体管的阈值电压向正向漂移, 最终使晶体管的工作模式由耗尽型转变为增强型. 关键词： 薄膜晶体管 无结 氧化铟锌 氧分子     

Spectroscopic characterization of Yb:Sc₂O₃ transparent ceramics

Yb:Sc2O3 transparent ceramics are fabricated by a conventional ceramic process and sintering in H2 atmosphere. The room-temperature spectroscopic properties are investigated, and the Raman spectrum shows an obvious vibration characteristic band centred at 415 cm 1 . There are three broad absorption bands around 891, 937, and 971 nm, respectively. The strongest emission peak is centred at 1.04 μm with a broad bandwidth (11 nm) and an emission cross-section of 1.8×10 20 cm 2 . The gain coefficient implies a possible laser ability in a range from 990 nm to 1425 nm. The energy-level structure shows that Yb:Sc 2 O 3 ceramics have large Stark splitting at the ground state level due to their strong crystal field. All the results show that Yb:Sc2O3 transparent ceramics are a promising material for short pulse lasers.     

Influence of a two-dimensional electron gas on current-voltage characteristics of Al_0.3Ga_0.7 N/GaN high electron mobility transistors

The J-V characteristics of AltGa1 tN/GaN high electron mobility transistors(HEMTs) are investigated and simulated using the self-consistent solution of the Schro¨dinger and Poisson equations for a two-dimensional electron gas(2DEG) in a triangular potential well with the Al mole fraction t = 0.3 as an example.Using a simple analytical model,the electronic drift velocity in a 2DEG channel is obtained.It is found that the current density through the 2DEG channel is on the order of 1013 A/m2 within a very narrow region(about 5 nm).For a current density of 7 × 1013 A/m2 passing through the 2DEG channel with a 2DEG density of above 1.2 × 1017 m-2 under a drain voltage Vds = 1.5 V at room temperature,the barrier thickness Lb should be more than 10 nm and the gate bias must be higher than 2 V.     

Interface-related switching behaviors of amorphous Pr_0.67Sr_0.33MnO₃-based memory cells

The resistive switching properties in amorphous Pr0.67Sr0.33MnO3 films deposited by pulsed laser deposition are investigated.Reproducible and bipolar counter-8-shape and 8-shape switching behaviours of Au/Pr0.67Sr0.33MnO3 /F:SnO2 junctions are obtained at room temperature.Dramatically,the coexistence of two switching polarities could be reversibly adjusted by an applied voltage range.The results allocated those two switching types to areas of different defect densities beneath the same electrode.The migration of oxygen vacancies and the trapping effect of electrons under an applied electric field play an important role.An interface-effect-related resistance switching is proposed in an amorphous Pr0.67Sr0.33MnO3-based memory cell.     

The research on suspended ZnO nanowire field-effect transistor

This paper reports that a novel type of suspended ZnO nanowire field-effect transistors (FETs) were successfully fabricated using a photolithography process, and their electrical properties were characterized by I--V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors (FET). The fabricated suspended nanowire FETs showed a p-channel depletion mode, exhibited high on--off current ratio of ～10⁵. When V_DS=2.5 V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage V_TH was about 0.6 V, the electron mobility was on average 50.17 cm²/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96× 10²Ω cm at V_GS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.     

Characterization of ZnO nanowire field-effect transistors and exposed to ultraviolet radiation

A ZnO nanowire (NW) field-effect transistor (FET) is fabricated and characterized, and its characterization of ultraviolet radiation is also investigated. On the one hand, when the radiation time is 5~min, the radiation intensity increases to 5.1~μ W/cm², while the saturation drain current (I_\rm dss) of the nanowire FET decreases sharply from 560 to 320~nA. The field effect mobility (μ ) of the ZnO nanowire FET drops from 50.17 to 23.82~cm²/(V.s) at V_\rm DS=2.5~V, and the channel resistivity of the FET increases by a factor of 2. On the other hand, when the radiation intensity is 2.5~μ W/cm^2 , the DC performance of the FET does not change significantly with irradiation time (its performances at irradiation times of 5 and 20~min are almost the same); in particular, the I_\rm dss of NW FET only reduces by about 50~nA. Research is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.     

High temperature thermoelectric properties of highly c-axis oriented Bi₂Sr₂Co₂O_y thin films fabricated by pulsed laser deposition

High-temperature thermoelectric transport property measurements have been performed on the highly c-axis oriented Bi2Sr2Co2Oy thin films prepared by pulsed laser deposition on LaAlO3(001).Both the electric resistivity ρ and the seebeck coefficient S of the film exhibit an increasing trend with the temperature from 300 K-1000 K and reach up to 4.8 m·Ω· cm and 202 μV/K at 980 K,resulting in a power factor of 0.85 mW/mK which are comparable to those of the single crystalline samples.A small polaron hopping conduction can be responsible for the conduction mechanism of the film at high temperature.The results demonstrate that the Bi2Sr2Co2Oy thin film has potential application in high temperature thin film thermoelectric devices.     

Breakdown voltage analysis of Al_0.25Ga_0.75N/GaN high electron mobility transistors with partial silicon doping in the AlGaN layer

In this paper,two-dimensional electron gas(2DEG) regions in AlGaN/GaN high electron mobility transistors(HEMTs) are realized by doping partial silicon into the AlGaN layer for the first time.A new electric field peak is introduced along the interface between the AlGaN and GaN buffer by the electric field modulation effect due to partial silicon positive charge.The high electric field near the gate for the complete silicon doping structure is effectively decreased,which makes the surface electric field uniform.The high electric field peak near the drain results from the potential difference between the surface and the depletion regions.Simulated breakdown curves that are the same as the test results are obtained for the first time by introducing an acceptor-like trap into the N-type GaN buffer.The proposed structure with partial silicon doping is better than the structure with complete silicon doping and conventional structures with the electric field plate near the drain.The breakdown voltage is improved from 296 V for the conventional structure to 400 V for the proposed one resulting from the uniform surface electric field.     

不同晶面的氢终端单晶金刚石场效应晶体管特性

通过微波等离子体化学气相淀积技术生长单晶金刚石并切割得到(110)和(111)晶面金刚石片,以同批器件工艺制备两种晶面上栅长为6μm的氢终端单晶金刚石场效应管,从材料和器件特性两方面对两种晶面金刚石进行对比分析.(110)面和(111)面金刚石的表面形貌在氢终端处理后显著不同,光学性质则彼此相似.VGS=–4 V时,(111)金刚石器件获得的最大饱和电流为80.41 m A/mm,约为(110)金刚石器件的1.4倍;其导通电阻为48.51 W·mm,只有(110)金刚石器件导通电阻的67%.通过对器件电容-电压特性曲线的分析得到,(111)金刚石器件沟道中最大载流子密度与(110)金刚石器件差异不大.分析认为,(111)金刚石器件获得更高饱和电流和更低导通电阻,应归因于较低的方阻.     

双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

Reduced graphene oxide field-effect transistor with indium tin oxide extended gate for proton sensing

In this study, the reduced graphene oxide field-effect transistor (rGO FET) with indium tin oxide (ITO) extended gate electrode was demonstrated as a transducer for proton sensing application. In this structure, the proton sensing area of the ITO extended gate electrode is isolated from the active area of the rGO FET. The proton sensing properties based on the rGO FET transducer were analyzed. The rGO FET device with encapsulation by a tetratetracontane (TTC) layer showed good stability in electrolytic solutions. The device showed an ambipolar behavior with shifts in Dirac point as the pH of the electrolyte is varied. The pH sensitivity based on the Dirac point shift as a sensing parameter was about 43–50 mV/pH for a wide range of pH values from 2 to 12. The ITO extended gate rGO FET may be considered a potential transducer for sensing of H⁺ in electrolytes. Its sensing area can be modified further for various ions sensing applications.     

具有poly-Si$lt;sub$gt;1-$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;Ge$lt;sub$gt;$lt;i$gt;x$lt;/i$gt;$lt;/sub$gt;栅的应变SiGep型金属氧化物半导体场效应晶体管阈值电压漂移模型研究

针对具有poly-Si_1-xGe_x栅的应变SiGe p型金属氧化物半导体场效应晶体管(PMOSFET), 研究了其垂直电势与电场分布, 建立了考虑栅耗尽的poly-Si_1-xGe_x栅情况下该器件的等效栅氧化层厚度模型, 并利用该模型分析了poly-Si_1-xGe_x栅及应变SiGe层中Ge组分对等效氧化层厚度的影响. 研究了应变SiGe PMOSFET热载流子产生的机理及其对器件性能的影响, 以及引起应变SiGe PMOSFET阈值电压漂移的机理, 并建立了该器件阈值电压漂移模型, 揭示了器件阈值电压漂移随电应力施加时间、栅极电压、poly-Si_1-xGe_x栅及应变SiGe层中Ge组分的变化关系. 并在此基础上进行了实验验证, 在电应力施加10000 s时, 阈值电压漂移0.032 V, 与模拟结果基本一致, 为应变SiGe PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础. 关键词： 应变SiGep型金属氧化物半导体场效应晶体管 1-xGe_x栅')" href="#">poly-Si_1-xGe_x栅 热载流子 阈值电压     

Artificial Haldane gap material on a semiconductor chip

We show how nanostructuring of a metallic gate of a field-effect transistor (FET) converts the electron channel of an FET to an artificial Haldane chain with a gap in the energy spectrum. A specially designed gate structure creates a chain of triple quantum dot molecules. The electrons localized in the molecules realize a spin-half Heisenberg chain with spin–spin interactions alternating between ferromagnetic and antiferromagnetic. The quantum state of an FET is a semiconductor implementation of an integer spin-one antiferromagnetic Heisenberg chain with a unique correlated ground state and a finite energy gap, originally conjectured by Haldane.     

基于超薄Al2O3栅绝缘层的低工作电压IGZO薄膜晶体管及其在共源极放大器中的应用

随着薄膜晶体管(Thin-film transistor,TFT)在各类新兴电子产品中得到广泛应用,作为各类电子设备的关键组件,其工作电压和稳定性面临着巨大挑战。为了满足未来高度集成化、功能复杂的应用场合,实现其低工作电压和高稳定性就变得异常重要。我们在150 mm×150 mm大面积玻璃基底上,采用磁控溅射非晶铟镓锌氧化物(amorphous indium-gallium-zinc-oxide,a-IGZO)作为有源层,以原子层沉积(ALD)Al2O3为栅绝缘层,制备了底栅顶接触型a-IGZO TFT,并研究了50,40,30,20 nm超薄Al2O3栅绝缘层对TFT器件的影响。其中,20 nm超薄Al2O3栅绝缘层TFT具有最优综合性能:1 V的低工作电压、接近0 V的阈值电压和仅为65.21 mV/dec的亚阈值摆幅,还具有15.52 cm^2/(V·s)的高载流子迁移率以及5.85×10^7的高开关比。同时,器件还表现出优异的稳定性:栅极±5 V偏压1 h阈值电压波动最小仅为0.09 V以及优良的150 mm×150 mm大面积分布均一性。实现了TFT器件的低工作电压和高稳定性。最后,以该TFT器件为基础设计了共源极放大器,得到14 dB的放大增益。     

Suppression of the tunneling effect by shallow junctions in field-effect transistor

We study the quantum wave transport in nanoscale field-effect transistors. It has been shown that the tunneling effect between the source and the drain in an ultra-short channel transistor significantly degrades the control of the drain current by the gate. However, the tunneling effect is suppressed by reducing the depth of the source and drain junctions which is designated to suppress the short-channel effects concerning the cut-off characteristics of the field-effect transistor. The reduced junction depth confines the carriers in the direction (y -direction) perpendicular to the transport direction (x -direction). The matching of y -direction wavefunctions at regional boundaries suppresses the tunneling effect and normal FET current–voltage characteristics has been obtained, which explains theoretically the successful fabrication of nanoscale field-effect transistors.     

Improvement of Performance of HfS_2 Transistors Using a Self-Assembled Monolayer as Gate Dielectric

This work details a study based on HfS_(2 )transistors utilizing an n-octadecylphosphonic acid-based self-assembled monolayer(SAM)as the gate dielectric.The fabrication of the SAM-based two-dimensional(2D)material transistor is simple and can be used to improve the quality of the interface of air-sensitive 2D materials.In comparison to HfS_(2) transistors utilizing a conventional Al_2O_(3) gate insulator by atomic layer deposition,HfS_(2) transistors utilizing an SAM as the gate dielectric can reduce the operation region from 4 V to 2 V,enhance the field-effect mobility from 0.03 cm~2/Vs to 0.75 cm~2/Vs,improve the sub-threshold swing from 404 m V/dec to 156 m V/dec,and optimize the hysteresis to 0.03 V,thus demonstrating improved quality of the semiconductor/insulator interface.