Trapezoid mesa trench metal-oxide semiconductor barrier Schottky rectifier: an improved Schottky rectifier with better reverse characteristics

An improved structure of Schottky rectifier,called a trapezoid mesa trench metal-oxide semiconductor (MOS) barrier Schottky rectifier (TM-TMBS),is proposed and studied by two-dimensional numerical simulations.Both forward and especially better reverse I-V characteristics,including lower leakage current and higher breakdown voltage,are demonstrated by comparing our proposed TM-TMBS with a regular trench MOS barrier Schottky rectifier (TMBS) as well as a conventional planar Schottky barrier diode rectifier.Optimized device parameters corresponding to the requirement for high breakdown voltage are given.With optimized parameters,TM-TMBS attains a breakdown voltage of 186 V,which is 6.3% larger than that of the optimized TMBS,and a leakage current of 4.3×10 6 A/cm 2,which is 26% smaller than that of the optimized TMBS.The relationship between optimized breakdown voltage and some device parameters is studied.Explanations and design rules are given according to this relationship.     

Comprehensive study of a 4H–SiC MES–MOSFET

In this paper, we studied the enhancement of the breakdown voltage in the 4H–SiC MESFET–MOSFET (MES–MOSFET) structure which we have proposed in our previous work. We compared this structure with Conventional Bulk-MOSFET (CB-MOSFET) and Field plated Conventional Bulk-MOSFET (FCB-MOSFET) structures. The 4H–SiC MES–MOSFET structure consists of two additional schottky buried gates which behave like a Metal on Semiconductor (MES) at the interface of the active region and substrate. The motivation for this structure was to enhance the breakdown voltage by introducing a new technique of utilizing the reduced surface field (RESURF) concept. In our comparison and investigation we used a two-dimensional device simulator. Our simulation results show that the breakdown voltage of the proposed structure is 3.7 and 2.9 times larger than CB-MOSFET and FCB-MOSFET structures, respectively. We also showed that the threshold voltage and the slope of drain current (I_D) as a function of drain–source voltage (V_DS) for all the structures is the same.     

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-$K$/low-$K$ compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-$K$ and low-$K$ layers due to the different dielectric constants of high-$K$ and low-$K$ dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p-n junction interface is suppressed due to the effects of the high-$K$ dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance ($R_{\rm on, sp}$) of 2.07 m$\Omega\cdot$cm$^{2}$ and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm$^{2}$, and a low turn-on voltage of 0.6 V.     

A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor(UMOSFET) integrated with a Schottky rectifier is proposed.In this device,a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET.Specific on-resistances of 7.7 m.mm 2 and 6.5 m.mm 2 for the gate bias voltages of 5 V and 10 V are achieved,respectively,and the breakdown voltage is 61 V.The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET.     

Edge termination study and fabrication of a 4Hben SiC junction barrier Schottky diode

The 4H-SiC junction barrier Schottky (JBS) diodes terminated by field guard rings and offset field plate are designed, fabricated and characterized. It is shown experimentally that a 3-μm P-type implantation window spacing gives an optimum trade-off between forward drop voltage and leakage current density for these diodes, yielding a specific on-resistance of 8.3 mΩ·cm². A JBS diode with a turn-on voltage of 0.65 V and a reverse current density less than 1 A/cm² under 500 V is fabricated, and the reverse recovery time is tested to be 80 ns, and the peak reverse current is 28.1 mA. Temperature-dependent characteristics are also studied in a temperature range of 75 ℃-200 ℃. The diode shows a stable Schottky barrier height of up to 200 ℃ and a stable operation under a continuous forward current of 100 A/cm².     

Research on high-voltage 4H-SiC P-i-N diode with planar edge junction termination techniques

The planar edge termination techniques of junction termination extension (JTE) and offset field plates and field-limiting rings for the 4H-SiC P-i-N diode were investigated and optimized by using a two-dimensional device simulator ISE-TCAD10.0. By experimental verification, a good consistency between simulation and experiment can be observed. The results show that the reverse breakdown voltage for the 4H-SiC P-i-N diode with optimized JTE edge termination can accomplish near ideal breakdown voltage and much lower leakage current. The breakdown voltage can be near 1650 V, which achieves more than 90 percent of ideal parallel plane junction breakdown voltage and the leakage current density can be near 3 × 10-5 A/cm2.     

n,p柱宽度对超结SiGe功率二极管电学特性的影响

结合SiGe材料的优异性能与超结结构在功率器件方面的优势,提出了一种超结SiGe功率二极管.该器件有两个重要特点:一是由轻掺杂的p型柱和n型柱相互交替形成超结结构,取代传统功率二极管的n^-基区;二是阳极p⁺区采用很薄的应变SiGe材料.该二极管可以克服常规Si p⁺n^-n⁺功率二极管存在的一些缺陷,如阻断电压增大的同时,正向导通压降随之增大,反向恢复时间也变长.利用二维器件模拟软件MEDICI仿真 关键词： 超结 锗硅二极管 n p柱宽度 电学特性     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

Experimental and numerical analyses of high voltage 4H-SiC junction barrier Schottky rectifiers with linearly graded field limiting ring

This paper describes the successful fabrication of 4H-SiC junction barrier Schottky(JBS) rectifiers with a linearly graded field limiting ring(LG-FLR). Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2(about 80% of the theoretical value). Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termination, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.     

A novel planar vertical double-diffused metal-oxide- semiconductor field-effect transistor with inhomogeneous floating islands

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (R_on,sp), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its R_on,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and R_on,sp are investigated, and the optimized results with BV of 83 V and R_on,sp of 54 mOmega cdotmm² are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior “R_on,sp/BV” trade-off to the conventional VDMOS (a 38% reduction of R_on,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of R_on,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively.     

Ni/4H-SiC肖特基势垒二极管的γ射线辐照效应

对制备的Ni/4H-SiC肖特基势垒二极管（SBD）进行了γ射线辐照试验,并在辐照过程中对器件分别加0和-30?V偏压.经过1?Mrad（Si）总剂量的γ射线辐照后,不同辐照偏压下的Ni/4H-SiC肖特基接触的势垒高度和理想因子没有退化,SiC外延层中的少子寿命也没有退化.辐照后器件的反向电流下降,这是由于器件表面的负界面电荷增加引起的.研究表明,辐照偏压对Ni/4H-SiC SBD的辐照退化效应没有明显的影响. 关键词： 碳化硅 肖特基 辐照效应 偏压     

An AlGaN/GaN HEMT with enhanced breakdown and near-zero breakdown voltage temperature coefficient

An AlGaN/GaN high-electron mobility transistor (HEMT) with a novel source-connected air-bridge field plate (AFP) is experimentally verified. The device features a metal field plate that jumps from the source over the gate region and lands between the gate and drain. When compared to a similar size HEMT device with conventional field plate (CFP) structure, the AFP not only minimizes the parasitic gate to source capacitance, but also exhibits higher OFF-state breakdown voltage and one order of magnitude lower drain leakage current. In a device with a gate to drain distance of 6 μm and a gate length of 0.8 μm, three times higher forward blocking voltage of 375 V was obtained at V_GS=-5 V. In contrast, a similar sized HEMT with CFP can only achieve a breakdown voltage no higher than 125 V using this process, regardless of device dimensions. Moreover, a temperature coefficient of 0 V/K for the breakdown voltage is observed. However, devices without field plate (no FP) and with optimized conventional field plate (CFP) exhibit breakdown voltage temperature coefficients of -0.113 V/K and -0.065 V/K, respectively.     

Prebreakdown condition in selenium rectifiers

This paper reports data from an experimental investigation of the prebreakdown and breakdown conditions of factory production selenium rectifiers in the temperature range from 100 ° to –196 ° C when a unit voltage pulse with steep leading edge (rise time about 10^–8 sec) is applied to the rectifier in the non-conducting direction. Change in voltage across the rectifier and in current through it were recorded by a two-channel high-speed electronic oscilloscope. On the basis of this test data, the variation of discharge rise-time in the selenium p-n junction as a function of overvoltage and temperature was determined, the formation of current pulses was detected in the junction, both before and during breakdown in the temperature range from 100 ° to –196 ° C, and it was also established that breakdowns of selenium rectifier p-n junctions are due to joint action of the Zener effect and impact ionization.We are indebted to Prof. Kh. I. Amirkhanov for his constant interest in this work.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.     

Al2O3介质层厚度对AlGaN/GaN金属氧化物半导体-高电子迁移率晶体管性能的影响

在蓝宝石衬底上采用原子层淀积法制作了三种不同Al₂O₃介质层厚度的绝缘栅高电子迁移率晶体管.通过对三种器件的栅电容、栅泄漏电流、输出和转移特性的测试表明：随着Al₂O₃介质层厚度的增加,器件的栅控能力逐渐减弱,但是其栅泄漏电流明显降低,击穿电压相应提高.通过分析认为薄的绝缘层能够提供大的栅电容,因此其阈值电压较小,但是绝缘性能较差,并不能很好地抑制栅电流的泄漏;其次随着介质厚度的增加,可以对栅极施加更高的正偏压,因此获 关键词： 2O₃')" href="#">Al₂O₃ 金属氧化物半导体-高电子迁移率晶体管 介质层厚度 钝化     

CVD法制备p-ZnO薄膜/n-Si异质结发光二极管及其性能研究

利用简单的化学气相沉积方法, 首先在n-Si衬底上生长Sb掺杂p-ZnO薄膜, 并在此基础上制作了p-ZnO/n-Si异质结发光二极管．对制备的Sb掺杂ZnO薄膜 在800 ℃下进行了热退火处理, 发现退火后样品的晶体质量和表面形貌都得到明显提高, 并且薄膜呈现的电导类型为p型, 载流子浓度为9.56× 10¹⁷ cm^-3. 此外, 该器件还表现出良好的整流特性, 正向开启电压为4.0 V, 反向击穿电压为9.5 V. 在正向45 mA的注入电流条件下, 器件实现了室温下的电致发光. 这说明较高质量的ZnO薄膜也可以通过简单的化学气相沉积方法来实现, 这为ZnO基光电器件的材料制备提供了一种简单可行的方法. 关键词： CVD p-ZnO 异质结 电致发光     

Ultraviolet electroluminescence from ZnO-based light-emitting diode with p-ZnO:N/n-GaN:Si heterojunction structure

A p-ZnO:N/n-GaN:Si structure heterojunction light-emitting diode (LED) is fabricated on c-plane sapphire by full metal organic chemical vapor deposition (MOCVD) technique. The p-type layer with hole concentration of 8.94×10¹⁶ cm⁻³ is composed of nitrogen-doped ZnO using NH₃ as the doping source with subsequent annealing in N₂O plasma ambient. Silicon-doped GaN film with electron concentration of 1.15×10¹⁸ cm⁻³ is used as the n-type layer. Desirable rectifying behavior is observed from the current-voltage (I-V) curve of the device. The forward turn on voltage is about 4 V and the reverse breakdown voltage is more than 7 V. A distinct ultraviolet (UV) electroluminescence (EL) with a dominant emission peak centered at 390 nm is detected at room temperature from the heterojunction structure under forward bias conditions. The origins of the EL emissions are discussed in comparison with the photoluminescence (PL) spectra.     

A novel double-recessed 4H-SiC MESFET with partly undoped space region

In this paper, a novel double-recessed 4H-SiC metal semiconductor field effect transistor (MESFET) with partly undoped space region (DRUS-MESFET) is introduced. The key idea in this work is to improve the DC and RF characteristics of the device by introducing an undoped space region. Using two-dimensional and two-carrier device simulation, we demonstrate that breakdown voltage (V_BR) increases from 109 V in conventional double recessed MESFET (DR-MESFET) structure to 144.5 V in the DRUS-MESFET structure due to the modified channel electric field distribution of the proposed structure. The maximum output power density of the DRUS-MESFET structure is about 25.4% larger than that of the DR-MESFET structure. Furthermore, lower gate-drain capacitance (C_GD), higher cut-off frequency (f_T), larger maximum available gain (MAG), and higher maximum oscillation frequency (f_max) are achieved for the DRUS-MESFET structure. The results show that the f_max and f_T of the proposed structure improve 95.6% and 13.07% respectively, compared with that of the DR-MESFET structure. Also, the MAG of the DRUS-MESET is 4.5 dB higher than that of the DR-MESFET structure at 40 GHz. The results show that the DRUS-MESFET structure has superior electrical characteristics and performances in comparison with the DR-MESFET structure.     

电荷耦合效应对高耐压沟槽栅极超势垒整流器击穿电压的影响

通过沟槽结构和可调节的电子势垒,沟槽栅极超势垒整流器可以更为有效地实现通态压降和反向漏电流之间的良好折衷.在高压应用时,电荷耦合效应对于提高该器件的反向承压能力起到了关键作用.本文通过理论模型与器件模拟结果,分析了沟槽深度、栅氧厚度和台面宽度等关键参数对电荷耦合作用下二维电场分布的影响,归纳出了提高该器件击穿电压的思路与方法,为器件设计提供了有意义的指导.在此基础上,提出了阶梯栅氧结构,该结构在维持几乎相同击穿电压的同时,使正向导通压降降低51.49%.     

Fabrication and characterization of p-ZnO/n-Zn0.8Cd0.2O/n-ZnO heterojunction

We report the fabrication of p-ZnO/n- Zn_0.8Cd_0.2O/n-ZnO heterojunctions that contain Al–N codoped p-ZnO, undoped n- Zn_0.8Cd_0.2O, and Al-doped n-ZnO layers. An InZn alloy is used as the p- and n-ZnO Ohmic contact electrodes. This structure exhibits improved rectifying p–n junction behavior, with forward turn-on voltage in the range of 3–5 V. The reverse breakdown voltage can be as high as 15 V, with 10^?6-A reverse leakage current. Photoluminescence spectra show strong near band-edge emissions for both p- and n-ZnO at 368 nm and for undoped n- Zn_0.8Cd_0.2O, which is substantially red-shifted to 399 nm.