A High Temperature Micropower Capacitive Pressure Sensor Interface Circuit

A pressure sensor interface circuit featuring micropower consumptionis presented. The sensitivity to leakage currents has been reduced, allowingoperation at high temperature. Special attention has been paid to minimisealiasing in the sampled interface. An optimal combination of contradictoryrequirements on power consumption, temperature range and sampling speed wasobtained by a very careful system design and optimisation. The circuitconverts a sensor capacitance variation of ±5pF into an 11 bit outputword at a 2Hz rate. This resolution is guaranteed in the –40°C to100°C temperature range. It may slowly decay above 100°C but ensuresat least 5 bit at 130°C. The power consumption at room temperature issmaller than 2µA from a 2.4V to 4V battery.     

地震勘探用电容式闭环微加速度计的仿真

MEMS加速度传感器大幅提高了新型地震检波器的各项性能指标。利用有限元软件AN-SYS建立了悬臂硅梁的力学模型,并通过其力学性能仿真,得出优化的设计结构尺寸,即梁长L=150μm,梁宽b=40μm,梁厚h=4μm,活动电极和固定电极的间距d0取为1μm。同时利用电路仿真软件建立了传感器闭环系统的整体仿真数学模型,仿真结果表明其阶跃响应和正弦响应基本和理论分析结果吻合,传感器的分辨率可达0.001 m/s2,频带宽度可达500 MHz。该基于MEMS加速度传感器的新型地震检波器在地震勘探中将具有广阔的应用前景。     

一种用于消化道酸碱度监测的传感器接口芯片

介绍了一款用于消化道酸碱度监测的专用接口集成电路芯片。该电路包含了信号放大电路、模数转化电路等,可以同时测量温度信号。芯片采用0.18 μm CMOS工艺实现,芯片大小仅为0.6 mm×0.4 mm,配合酸碱度传感电极和无线收发模块可制成消化道无线监测智能胶囊。对该芯片进行测试,结果显示,电路工作状态良好,可精确地采集信号,酸碱度检测的精度可以达到±0.1 pH,温度检测精度可达±0.2 ℃。     

一种新的不受寄生电容影响的电容式传感器接口电路

给出了一种新的用于微小电容检测的接口电路 .在电荷传送电路的基础上,引入了一个用于参考微变电容读出的电荷传送电路部分,将检测电路与参考电路的输出进行差分放大,从而大大提高了电路的稳定性和检测灵敏度,同时此电路也保持了电荷传送电路检测微小电容变化不受寄生电容影响的特性.     

一种新的不受寄生电容影响的电容式传感器接口电路

给出了一种新的用于微小电容检测的接口电路 .在电荷传送电路的基础上,引入了一个用于参考微变电容读出的电荷传送电路部分,将检测电路与参考电路的输出进行差分放大,从而大大提高了电路的稳定性和检测灵敏度,同时此电路也保持了电荷传送电路检测微小电容变化不受寄生电容影响的特性.     

Low-Cost CMOS Interface for Capacitive Sensors and Its Application in a Capacitive Angular Encoder

A low-cost CMOS integrated interface for capacitivesensors is presented. The interface is composed of two separatechips: a capacitance-controlled oscillator and a selector, whichresult in a structure that is able to measure several capacitancesaccurately and has a microcontroller-compatible output. In thisinterface, even large parasitic capacitances of up to 3 nF betweenthe terminals of the capacitor to be measured and ground areallowed. Prototypes of the interface chips have been fabricatedin a 0.7-µm CMOS process. The frequency of theoscillator amounts to 90 kHz. For the capacitance measurement,the interface has a resolution of 11.3 ppm and a nonlinearityof 300 ppm over a measurement range of 2 pF. In this paper, alsothe application of the interface in an accurate capacitive angularencoder is discussed.     

A 12-Bit Ratio-Independent Algorithmic A/D Converter for a Capacitive Sensor Interface

This paper describes a ratio-independent algorithmic analog-digital (A/D) converter architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40-kS/s A/D converter (ADC) with an active die area of 0.041 mm² is implemented in a 0.13-mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4-muW power dissipation, the ADC achieves 80.2-dB spurious-free dynamic range and 63.3-dB signal-to-noise and distortion ratio.     

A Universal Transducer Interface for Capacitive and Resistive Sensor Elements

This paper presents a new universal transducer interface.This interface, which is read out by a microcontroller, servicesthe following sensor elements: capacitors, platinum resistors,thermistors, resistive bridges and potentiometers. The A/D conversionis based on a first-order oscillator. A combination of classicaland some new measurement techniques has been applied on a singlechip to obtain high accuracy, good long-term stability and areduction of the effects of interference and parasitic elements.The circuit has been fabricated in a 0.7 µm CMOSprocess. The main test results are: an accuracy of 10–15bits and a resolution up to 16 bits while the measurement timeis in the range 1–100ms. These results hold over the temperaturerange –20°C to 80°C. Calibrationof the electronic part is not required. The number of externalcomponents has been kept to a minimum.     

A Charge-Based Low-Power High-SNR Capacitive Sensing Interface Circuit

This paper describes a low-power approach to capacitive sensing that achieves a high signal-to-noise ratio (SNR). The circuit is composed of a capacitive feedback charge amplifier and a charge adaptation circuit. Without the adaptation circuit, the charge amplifier only consumes 1 $~mu hbox{W}$ to achieve the audio band SNR of 69.34 dB. An adaptation scheme using Fowler–Nordheim tunneling and channel hot-electron injection mechanisms to stabilize the dc output voltage is demonstrated. This scheme provides a very low frequency pole at 0.2 Hz. The measured noise spectrums show that this slow-time scale adaptation does not degrade the circuit performance. The dc path can also be provided by a large feedback resistance without causing extra power consumption. A charge amplifier with a MOS-bipolar pseudo-resistor feedback scheme is interfaced with a capacitive micromachined ultrasonic transducer to demonstrate the feasibility of this approach for ultrasound applications.      

Ultra-Low-Power Interface Chip for Autonomous Capacitive Sensor Systems

Traditionally, most of the sensor interfaces must be tailored towards a specific application. This approach results in a high recurrent design cost and time to market. On the other hand, generic sensor interface design reduces the costs and offers a handy solution for multisensor applications. This paper presents a generic sensor interface chip (GSIC), which can read out a broad range of capacitive sensors. It contains capacitance-to-voltage converters, a switched-capacitor amplifier, an analog-to-digital converter, oscillators, clock generation circuits and a reference circuit. The system combines a very low-power design with a smart energy management, which adapts the current consumption according to the accuracy and speed requirements of the application. The GSIC is used in a pressure and an acceleration monitoring system. The pressure monitoring system achieves a current drain of 2.3 muA for a 10-Hz sample frequency and an 8-bit accuracy. In the acceleration monitoring system, we measured a current of 3.3 muA for a sample frequency of 10 Hz and an accuracy of 9 bits     

电容式微加速度计模拟前端接口电路设计

基于连续时问的全差分电容结构,设计了一款电容式微加速度计模拟前端接口电路。该电路采用了斩波稳定技术,减小了运算放大器的直流偏差和闪烁噪声,同时,引入了一种周期复位的方法来稳定电压电容转换器输入端口求和节点的直流偏置,并实现了灵敏度可调的功能。该设计在TSMC0．35Hm工艺下流片,面积为3．4mm2。测试结果表明,在5V供电电压下,电路非线性度小于O．7％,功耗约9．4mW。     

新型电容式MEMS加速度计数字接口电路设计

MEMS加速度计接口电路主要采用传统sigma-delta架构实现,但这种方式中的电路失调电压很容易产生积分饱和现象．为解决这个问题,本文设计了一种可以用于钻井、石油勘探等微弱信号检测的新型数字电容接口电路．该设计在电容式MEMS加速度传感器基础上,采用FPGA实现数字三阶环路滤波器,构成5阶sigma-delta系统．采用数字环路滤波器降低了ASIC模拟电路版图设计与芯片测试难度,利于快速优化环路滤波器设计参数,改善系统稳定性和优化系统噪声性能．前置放大器采用一种相对简单的相关双采样技术,能够有效减小前置放大器的失调电压．根据MEMS加速度计前置放大器输出信号符合正态分布的特点,设计了带有一定预测功能的8-bit瞬时浮点ADC,实现模拟与数字环路滤波器互联．在200Hz带宽内,该接口电路系统噪声基底达到53．09ng／rt（Hz）,满足系统噪声设计要求．前置放大器与ADC采用XFAB XH018混合信号CMOS工艺流片,开环测试表明,前置放大器的灵敏度和噪声分别为0．69V／pF和3．20μV／rt（Hz）．     

MEMS陀螺仪驱动接口ASIC设计

基于0.18 μm CMOS工艺,设计了一种用于MEMS陀螺仪驱动闭环的专用集成电路,实现了MEMS陀螺仪的高精度、集成式和数字化驱动。陀螺仪采用静电力驱动,基于自激振荡原理,结合自动增益控制方法,实现了恒幅恒频振动。设计了电容/电压转换器、3阶带通Σ-Δ ADC等模拟前端电路。芯片测试结果表明,陀螺仪成功起振,谐振频率为3.7 kHz,启动时间≤0.3 s,驱动检测信号的信噪比达到115 dB,驱动振幅1 h稳定性为1.5×10-4,整个芯片的功耗小于20 mW,电路性能良好。     

单片集成MEMS电容式压力传感器接口电路设计

介绍了一种单片集成电容式压力传感器接口电路，该电路基于电容一频率转化原理，并通过差频消除了温度变化和工艺波动对电路性能的影响。使用Pspice对接口电路的误差特性进行了分析，并依据仿真结果确定了电路的相关参数。最后给出电路的测试结果，测试结果与仿真结果一致，在80～110kPa量程内，接口电路的分辨率为3．77Hz／hPa。     

单片集成MEMS电容式压力传感器接口电路设计

介绍了一种单片集成电容式压力传感器接口电路,该电路基于电容-频率转化原理,并通过差频消除了温度变化和工艺波动对电路性能的影响。使用Pspice对接口电路的误差特性进行了分析,并依据仿真结果确定了电路的相关参数。最后给出电路的测试结果,测试结果与仿真结果一致,在80~110kPa量程内,接口电路的分辨率为3.77Hz/hPa。     

Micropower active-RC channel filter for a zero-IF Bluetooth receiver

A fourth-order low-pass channel filter for a zero-IF Bluetooth receiver is presented. It employs two cascaded multiple feedback biquads and active resistors made by quasi-floating gate MOS transistors in triode region for highly linear continuous tuning. Power consumption is strongly reduced using a gain-enhanced class-AB single-stage opamp together with a filter topology that only requires a single opamp for each biquad. The filter has been fabricated in a 0.18 μm CMOS technology and consumes 290 μW from a 1.2 V supply.     

A Low-Power Stand-Alone Adaptive Circuit for Harvesting Energy From a Piezoelectric Micropower Generator

An adaptive energy-harvesting circuit with low power dissipation is presented and demonstrated, which is useful for efficient ac/dc voltage conversion of a piezoelectric micropower generator. The circuit operates stand-alone, and it extracts the piezoelectric strain energy independent of the load and piezoelectric parameters without using any external sensor. The circuit consists of a voltage-doubler rectifier, a step-down switching converter, and an analog controller operating with a single supply voltage in the range of 2.5–15 V. The controller uses the piezoelectric voltage as a feedback and regulates the rectified voltage to adaptively improve the extracted power. The nonscalable power dissipation of the controller unit is less than 0.05 mW, and the efficiency of the circuit is about 60% for output power levels above 0.5 mW. Experimental verifications of the circuit show the following: 1) the circuit notably increases the extracted power from a piezoelectric element compared to a simple full-bridge diode rectifier without control circuitry, and 2) the efficiency of the circuit is dominantly determined by its switching converter. The simplicity of the circuit facilitates the development of efficient piezoelectric energy harvesters for low-power applications such as wireless sensors and portable devices.      

A conceptual framework for ASIC design

An attempt is made to gain a better understanding of the nature of ASIC (application-specific integrated circuit) design. This is done from a decision-making perspective, in terms of three knowledge frames: the design process, the design hyperspace, and the design repertoire. The design process frame emphasizes the hierarchical design approach and presents the methodology as a formalization of the design process. The design hyperspace concept relates to the recognition of design alternatives. Analysis techniques for evaluating algorithmic and architectural alternatives are collected and classified to form the design repertoire. This conceptual framework is an effective instrument for bridging the widening gap between system designers and VLSI technology. It also provides a conceptual platform for the development of tools for high-level architectural designs     

一款深亚微米ASIC芯片的后端设计

采用0.18μm及以下工艺设计高性能的VLSI芯片面临着诸多挑战,如特征尺寸缩小带来的互联线效应、信号完整性对芯片时序带来的影响、时序收敛因为多个设计变量的相互信赖而变得相当复杂,使芯片版图设计师需深入介入物理设计,选用有效的EDA工具,结合电路特点开发有针对性的后端设计流程。文章介绍了采用Cadence公司Soc Encounter后端工具对基于0.18μm工艺的ASIC芯片后端设计过程,分为后端设计前的数据准备、布局规划、电源设计、单元放置及优化、时钟树综合、布线等几个阶段进行了重点介绍。同时考虑到深亚微米工艺下的互联线效应,介绍了如何预防串扰问题,以及在整个布局布线过程中如何保证芯片的时序能够满足设计要求。     

一种新型三谐振点电容式RF MEMS开关

给出了改进的电容式开关等效电路模型以及基于该电路模型的一种新型的多频段工作的电容式RFM EM S开关的设计和制作研究。分析表明,当开关的上电极为多支撑梁结构时,需要对传统的开关等效电路加以改进。利用新型等效电路模型进行模拟发现,通过适当的参数选择,可以获得多谐振点开关,不仅可以在多个频段适用,并且可以适用于较低频段。设计了一种可工作在X波段下的三谐振点电容式RF MEMS开关,并在高阻硅衬底上采用表面微加工工艺制备了开关样品。三谐振点开关的在片测试结果为:驱动电压为7 V,“开”态的插入损耗为0.69 dB@10.4 GHz,“关”态的隔离度为30.8 dB@10.4 GHz,其微波性能在0~13.5 GH z频段下优于类似结构的传统单谐振点开关。