Transversal-readout architecture for CMOS active pixel image sensors

Novel architecture for CMOS active pixel image sensors (APSs), which eliminates the vertically striped fixed pattern noise (FPN), is presented. There are two kinds of FPN for CMOS APSs. One originates from the pixel-to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which results in a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and column-reset transistor, a source-follower input transistor, and a column-select transistor instead of the row-select transistor found in conventional CMOS APSs. The column-select transistor is connected to a signal line that runs horizontally instead of vertically. An experimentally fabricated 320/spl times/240-pixel CMOS APS employing the transversal-readout architecture exhibited neither vertically nor horizontally striped FPN. A buried-photodiode device with the transversal-readout architecture is also proposed.     

Low-cost sound-based localization using programmable mixed-signal systems-on-chip

There have been extensive theoretical studies on sound-based localization using both, a pair of microphones and microphone arrays. In contrast, there has been much less work on implementing and experimenting sound-based localization realized as customized electronic designs. This paper presents a low-cost implementation of the sound-based localization method proposed in Halupka et al. [11]. A new method called wave counting is proposed in this paper, as an alternative to the Maximum Likelihood procedure used in [11]. The implementation uses PSoC programmable mixed-signal embedded system-on-chip, which incorporates microcontroller, on-chip SRAM and flash memory, programmable digital blocks, and programmable analog blocks, all integrated on the same chip. The paper presents an extensive set of experiments to characterize the quality of localization using the proposed low-cost design.     

An architecture for a configurable mixed-signal device

The mixed-signal programmable system-on-chip (PSOC) architecture for high-volume low-cost applications is presented. Programmable analog, digital, and clocking circuits are combined with flash memory and a microcontroller to provide a platform for single-chip solutions for low-cost consumer applications. Both programmable analog and digital circuits are designed to support a moderate level of abstraction, balancing flexibility against cost and performance. A rough comparison of alternative approaches based on functionality and cost is presented.     

A new device architecture suitable for high-resolution andhigh-performance image sensors

A device architecture for building high-performance and high-resolution image sensors suitable for consumer TV camera applications is introduced. The sensor elements are junction field-effect transistors that are organized in an array with their gates floating and capacitively coupled to common horizontal address line. The photogenerated signal is sampled one line at a time, processed to remove the element-to-element nonuniformities, and stored in a buffer for subsequent readout. The concept, which includes an intrinsic exposure control, is demonstrated on a test image sensor that has an 8-mm sensing area diagonal and 580 (H)×488 (V) pixels. The key performance parameters, in addition to a high packing density of sensing elements with a unique hexagonal shape, include high signal uniformity, low dark current, good light sensitivity, high blooming overload protection, and no image smear. The discussion covers the design and operation of the basic image-sensing element, the architecture of the array, and the operation of the on-chip circuits needed for addressing and processing of generated signals. The overall device performance is demonstrated by typical device characterization results     

A programmable architecture for OFDM-CDMA

Combining multicarrier (OFDM) and CDMA technologies is attractive for future wireless broadband communications and software radio realization. Based on the unified framework known as OFCDMA, we develop a programmable structure for OFDM-CDMA transceivers in spite of three different scenarios to combine OFDM and CDMA. By adjusting system parameters without changing the fundamental hardware and software architecture, various system scenarios can be implemented, which might serve as the foundation to design software radio     

MEMS传感器和智能传感器的发展

MEMS传感器和智能传感器可以被称为新时代传感器的典型代表,在智能化以及集成化方面体现出独特的优势。随着我国科学技术发展水平的提高,MEMS传感器和智能传感器也处于不断发展的过程中,同时应用的范围不断拓宽,为各行各业带来了极大的便利。文章对此展开分析。     

A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture

In this paper we propose a design of a dependable self-organizing and adaptive mixed-signal SoC. We introduce an Artificial Hormone System (AHS) as a general control mechanism, which addresses the goals of organic computing methodology. Regarding the coexistence of digital and analog components in SoCs, we developed two new AHS implementations, one pure analog approach and one mixed-signal approach. Besides the basics of the hormone based control mechanisms, especially for the analog domain, this paper adapts the AHS upon mixed-signal SoC and presents the evaluation of a completely simulated AHS-controlled SoC. This evaluation verifies the approaches including stability issues as well as upper timing bounds and shows the improvement achieved on the system reliability. We also state the advantages from the hormone system compared to other approaches, as well as the strong points of the different hormone systems to one another.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays （FPAAs）, which are the analogue counterparts of Field Programmable Gate Arrays （FPGAs）. In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory micro- system. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks （CABs） which house a variety of processing elements especially the proposed fine-grained Core Con- figurable Amplifiers （CCAs）. The high flexible CABs allow the FPAA operating in both continu- ous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.     

Service gateway architecture for a smart home

An implementation of the Open Service Gateway Initiative (OSGi) standard that enhances the standard and integrates many existing home protocols and home networks is presented. This enhancement extends the ideas behind the OSGi specification, allowing its direct application to real-life situations. Special emphasis is placed on realizing an effective and realistic gateway management system. The architecture presented was applied in several pilot projects     

Routing architecture optimizations for high-density embedded programmable IP cores

Programmable logic cores differ from stand-alone field-programmable gate arrays in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing architecture of rectangular programmable logic cores. We quantify the effects of having different X and Y channel capacities and show that the optimum ratio between the X and Y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Further, we quantify the effects of logic block pin placement. Compared with a simple extension of an existing switch block, our new architecture leads to a density improvement of up to 11.9%. Finally, we show that, if the channel width, switch block, and pin placement are chosen carefully, then the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 3.8%.     

A programmable architecture for the provision of hybrid services

The success of new service provision platforms will largely depend on their ability to blend with existing technologies. The advent of Internet telephony, although impressive, is unlikely to make telephone customers suddenly turn in favor of computers. Rather, customers display increasing interest in services that span multiple networks (especially Internet protocol-based networks and the telephone and cellular networks) and open new vistas. We refer to these services as hybrid services and propose an architecture for their provision. This architecture allows for programming the service platform elements (i.e., network nodes, gateways, control servers, and terminals) in order to include new service logics. We identify components that can be assembled to build these logics by considering a service as a composition of features such as address translation, security, call control, connectivity, charging, and user interaction. Generic service components are derived from the modeling of these features. We assure that our proposal can be implemented even in existing systems in return for slight changes. These systems are required to generate an event when a special service is encountered. The treatment of this event is handled by an object at a Java service layer. Java has been chosen for its platform-neutrality property and its embedded security mechanisms. Using our architecture, we design a hybrid closed user group service     

A policy-based management architecture for active and programmable networks

Next generation networks must be capable of supporting a multitude of service providers that exploit an environment in which services are dynamically deployed and quickly adapted over a common heterogeneous physical infrastructure, according to varying and sometimes conflicting customer requirements. In this context, network management must become more flexible in order to cope with these emerging conditions. More specifically, new management architectures must offer service providers the freedom to manage their services according to their own policies and seamlessly extend management functionality as the only way to react to the introduction of new services. Based on a new business model that describes such an environment, we propose a policy-based management architecture that is extensible and operates in an active and programmable network. This management architecture is part of a new network architecture that was developed in the FAIN European Union research and development IST project.     

Combined image signal processing for CMOS image sensors

An efficient image signal processing structure is proposed for CMOS image sensors to achieve low area and power consumption. In the proposed structure, the gamma correction block is moved to the front to merge several image signal processings into one block. An efficient compensation scheme is also proposed to reduce the errors caused by the moving of the nonlinear gamma correction. Experimental results show that the proposed structure reduces area and power consumption by 23.8 and 31.1%, respectively.     

A reconfigurable analog processor using coarse-grained,heterogeneous configurable analog blocks for field programmable mixed-signal processing

A field programmable analog array (FPAA), designed for a reconfigurable analog processor, introduces coarse-grained, heterogeneous configurable analog blocks that improves performance and power consumption. Designed in an SMIC standard 0.18 μm CMOS process, mixed-signal processing can be performed by the assistance of an on-chip MCU and configurable digital blocks. Relative precision of the analog processing is 99.5%. A PID controller is shown as an application example. With a total die area of 11 mm², the maximum power consumption is 17.6 mA with a 3.3 V supply voltage, resulting in a 17× improvement in energy-efficiency over current conventional FPAAs.     

A current mode active pixel with high sensitivity pinned PD in standard CMOS process for smart image sensors

In this paper we present a current mode structure for Active Pixel Sensor (APS) which is an essential part in fast Smart CMOS Image Sensors (SCIS). Using two diodes (N+/P-Well and P-Well/Deep-N-Well) in parallel like a Pinned Photo-Diode (PPD) improves sensing of optical signal and leads to higher sensitivity than a conventional Photo-Diode (PD). Also integrated signal amplification inside the collection area of the pixel increases the sensitivity of the device due to the amplification in the pixel. The proposed structure with regards to using Deep-N-Well/P-Substrate junction as a guard ring, suppresses the pixel Cross-Talk (CTK) highly. In pixel Delta Reset Sampling (DRS) architecture helps to make feasible on-chip parallel processing. A post layout simulation for test structure of the proposed current mode APS has been considered by standard 0.18 µm RF-CMOS technology of TSMC with a 10 µm×10 µm PD size. Fill factor of each pixel is 24%.     

CMOS image sensors

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most important advantages of CMOS image sensors over CCDs is the ability to integrate sensing with analog and digital processing down to the pixel level. Finally, we focus on recent developments and future research directions that are enabled by pixel-level processing, the applications of which promise to further improve CMOS image sensor performance and broaden their applicability beyond current markets.     

智慧工厂的信息物理融合系统体系结构设计

分析了CPS的概念、基本功能和特性,针对工厂的实际情况,提出一种CPS五层体系结构,包括泛在感知层、互联网络层、语义信息层、模型计算层、服务代理层。并对各个层次的关键技术和结构进行详细设计。通过一个卷烟工厂落地应用实例,证明了体系结构符合工厂的信息化水平和应用现状,对工厂走向智慧化起到基础性支撑作用。     

用于智能医疗监控的医疗大数据架构

智能可穿戴医疗设备所生成混杂结构化和非结构化的海量数据对医疗大数据分析平台的性能提出了巨大挑战,为此文中提出了一种面向医疗物联网的大数据架构。所提出的医疗大数据架构采用了公有云技术,包括两个主要的子架构,即雾计算架构和分组选择(GC)架构。雾计算架构使用Apache Pig和Apache HBase等大数据技术收集和存储从不同传感器设备生成的海量传感数据。GC架构用于确保雾计算与公有云的高效集成。将该框架应用于基于心脏疾病预测模型的健康系统,证明了所提出的架构在实验的数据吞吐量下具有良好的CPU计算性能和数据存储性能。