Silicon nanoparticle charge trapping memory cell

A charge trapping memory with 2 nm silicon nanoparticles (Si NPs) is demonstrated. A zinc oxide (ZnO) active layer is deposited by atomic layer deposition (ALD), preceded by Al₂O₃ which acts as the gate, blocking and tunneling oxide. Spin coating technique is used to deposit Si NPs across the sample between Al₂O₃ steps. The Si nanoparticle memory exhibits a threshold voltage (V_t) shift of 2.9 V at a negative programming voltage of –10 V indicating that holes are emitted from channel to charge trapping layer. The negligible measured V_t shift without the nanoparticles and the good re‐ tention of charges (>10 years) with Si NPs confirm that the Si NPs act as deep energy states within the bandgap of the Al₂O₃ layer. In order to determine the mechanism for hole emission, we study the effect of the electric field across the tunnel oxide on the magnitude and trend of the V_t shift. The V_t shift is only achieved at electric fields above 1 MV/cm. This high field indicates that tunneling is the main mechanism. More specifically, phonon‐assisted tunneling (PAT) dominates at electric fields between 1.2 MV/cm < E < 2.1 MV/cm, while Fowler–Nordheim tunneling leads at higher fields (E > 2.1 MV/cm). (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Carriers recombination processes in charge trapping memory cell by simulation

We have evaluated the effects of recombination processes in a charge storage layer, either between trapped electrons and trapped holes or between trapped carriers and free carriers, on charge trapping memory cell＇s performances by numerical simulation. Recombination is an indispensable mechanism in charge trapping memory. It helps charge convert process between negative and positive charges in the charge storage layer during charge trapping memory programming/erasing operation. It can affect the speed of programming and erasing operations.     

Effects of charge storage dielectric thickness on hybrid gadolinium oxide nanocrystal and charge trapping nonvolatile memory

The characteristics of hybrid gadolinium oxide nanocrystal (Gd₂O₃-NC) and gadolinium oxide charge trapping (Gd₂O₃-CT) memories were investigated with different Gd₂O₃ film thickness. By performing the rapid thermal annealing on Gd₂O₃ films with different thickness, the Gd₂O₃-NCs with the diameter of 6–9 nm for charge storage, surrounded by the amorphous Gd₂O₃ (α-Gd₂O₃) layer, were formed. The α-Gd₂O₃ layer was considered to be the charge trapping layer, resulting in the large memory window of Gd₂O₃-NC/CT memories with thick Gd₂O₃ film. The charge trapping energy level of the Gd₂O₃-NCs and α-Gd₂O₃ layer was extracted to be 0.16 and 0.45 eV respectively by using the temperature-dependent retention measurement. Further, after a 10⁶ program/erase cycling operation, the memory with thin Gd₂O₃ film can be predicted to sustain a 94% memory window of the first cycling one while the memory with thick Gd₂O₃ film suffered from a 30% charge loss because of the traps within the α-Gd₂O₃ layer. The Gd₂O₃ film thickness of 10 nm was optimized to exhibit superior performances of the Gd₂O₃-NC/CT memory, which can be applied into the nonvolatile memory.     

Investigation of light programmable non‐volatile memory in an organic phototransistor

Excellent non‐volatile memory characteristics have been demonstrated under the optoelectric conditions for organic phototransistors (OPTs). The high photosensitivity shown as reversible shifts in light‐induced V_TH exhibits a large memory window for programming caused by the excited immobile carriers (electron) trapped as a function of the electrical bias and the light intensity. The long life span of stored electrons also reveals promising behavior with respect to data retention as well as the electrical reliability to serve as a data storage medium with the non‐volatile memory characteristic in OPTs. The V_TH recovery accelerated by the reversible bias stress for the stored charges under irradiation shows that the erasing behavior is clearly brought by the discharge process of long‐lived electrons occupied in deep states. Plausible mechanisms in the energy band are discussed for the programming and erasing process, which provides a fundamental understanding of the intrinsic charge storage behavior in OPTs. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Random telegraph noise on the threshold voltage of multi-level flash memory

We investigate the impact of random telegraph noise (RTN) on the threshold voltage of multi-level NOR flash memory. It is found that the threshold voltage variation (ΔV_th) and the distribution due to RTN increase with the programmed level (V_th) of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.     

Electrical and material characterization of tantalum pentoxide (Ta2O5) charge trapping layer memory

In this experiment, tantalum pentoxide (Ta₂O₅) was used in a metal/oxide/high-k Ta₂O₅/oxide/silicon (MOHOS) novel nanocrystal memory as a trapping layer. Post-annealing treatment, which can passivate defects and improve the material quality of the high-k dielectric, was applied to optimize device performance for a better memory window and faster P/E (program/erase) cycle. Material and electrical characterization techniques including X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and electrical measurements were performed to analyze the device under different annealing conditions. The Ta₂O₅ charge trapping layer memory annealed at 900 °C had a higher window of 3.3 V in the current-voltage (C-V) hysteresis loop, and a higher charge retention capability than the samples prepared under various annealing conditions. These higher levels were due to the higher probability of deep-level charge trapping and lower leakage current.     

Statistical emission of electrons from nanocrystalline silicon quantum dot memory nodes in a few-electron MOSFET memory device

Operation of a short and narrow channel metal-oxide-semiconductor field-effect transistor (MOSFET) memory device with a few nanocrystalline Si (nc-Si) dots in the active region has been investigated at 300 and 30 K. The discrete shift of the threshold voltage (V_th) in the current-voltage characteristics that arises from the screening effect of the charge stored in the nc-Si dot above the FET channel, suggests memory operation. It is found that the value of V_th changes with temperature whereas the magnitude of the shift in V_th is independent of temperature. The lifetime of the electrons stored in the floating node has also been investigated at different read voltages.     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing(P/E) operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.     

Elastic properties of linear charge density wave materials in the regime of nonlinear conduction

The Young's moduli E of TaS₃, (TaSe₄)₂I, and NbSe₃ are found to soften when the samples are subjected to voltages V in excess of the threshold V_T for nonlinear electrical conduction by sliding charge density waves. The voltage dependences of E are similar to the voltage dependences of the differential resistance and of the dielectric constant. The difference in stiffness for V < V_T and V >> V_T is ascribed to decoupling of distortions of the charge density wave from those of the underlying lattice.     

Photo-induced charge transport in SiO2films containing Si nanocrystals

Photo-induced charge transport is reported in metal–insulator–semiconductor structures containing Si nanocrystals produced by ion implantion and annealing. Successive shifts in current–voltage (I–V) and capacitance–voltage (C–V) curves are shown to be induced by ultra-violet (UV) light exposure under no bias. These shifts are shown to be enhanced by the application of a negative bias voltage during illumination. The application of a positive bias voltage during illumination is shown to reverse the direction of the shifts in both the I–V and C–V curves. This behaviour can be explained by charging of the nanocrystals induced by photoionization of electrons and charge movements in the insulator layer.     

缺陷对电荷俘获存储器写速度影响

基于密度泛理论的第一性原理以及VASP软件,研究了电荷俘获存储器(CTM)中俘获层HfO2在不同缺陷下(3价氧空位(VO3)、4价氧空位(VO4)、铪空位(VHf)以及间隙掺杂氧原子(IO))对写速度的影响.对比计算了HfO2在不同缺陷下对电荷的俘获能、能带偏移值以及电荷俘获密度.计算结果表明:VO3,VO4与VHf为单性俘获,IO则是双性俘获,HfO2在VHf时俘获能最大,最有利于俘获电荷;VHf时能带偏移最小,电荷隧穿进入俘获层最容易,即隧穿时间最短;同时对电荷俘获密度进行对比,表明VHf对电荷的俘获密度最大,即电荷被俘获的概率最大.通过对CTM的写操作分析以及计算结果可知,CTM俘获层m-HfO2在VHf时的写速度比其他缺陷时的写速度快.本文的研究将为提高CTM操作速度提供理论指导.     

A new microcontroller-based RADFET dosimeter reader

A new reader for radiation dose measurements using RADFET (pMOSFET) dosemeters has been developed. The threshold voltage (V_T) of the pMOSFETs is measured using a “one-point” method that determines V_T as the gate voltage for a given drain current. Using V_T, the absorbed dose, which is directly proportional to the threshold voltage shift, is calculated. The reader is based on a low cost 8-bit PIC 18F4520 microcontroller (MCU), and works independently of a personal computer, uses a touch screen and stores the data in microcontroller memory. Good agreement in threshold voltage values, obtained using a high-quality source-measure unit and the reader, was obtained. In addition, the reader can be used for threshold voltage measurement with other types of MOSFETs, especially in long duration experiments, as well as for the real-time measurements in radiotherapy, either as an autonomous system or integrated in a larger monitoring configuration.     

Conductivity of single-walled carbon nanotubes

In a system of N interacting single-level quantum dots (QDs), we study the relaxation dynamics and the current–voltage characteristics determined by symmetry properties of the QD arrangement. Different numbers of dots, initial charge configurations, and various coupling regimes to reservoirs are considered. We reveal that effective charge trapping occurs for particular regimes of coupling to the reservoir when more than two dots form a ring structure with the C_N spatial symmetry. We reveal that the effective charge trapping caused by the C_N spatial symmetry of N coupled QDs depends on the number of dots and the way of coupling to the reservoirs. We demonstrate that the charge trapping effect is directly connected with the formation of dark states, which are not coupled to reservoirs due to the system spatial symmetry C_N. We also reveal the symmetry blockade of the tunneling current caused by the presence of dark states.     

High-performance amorphous In-Ga-Zn-O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO2 heterojunction charge trapping stack

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) memories with novel p-SnO/n-SnO₂ heterojunction charge trapping stacks (CTSs) are investigated comparatively under a maximum fabrication temperature of 280 ℃. Compared to a single p-SnO or n-SnO₂ charge trapping layer (CTL), the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention. Of the two CTSs, the tunneling layer/p-SnO/n-SnO₂/blocking layer architecture demonstrates much higher program efficiency, more robust data retention, and comparably superior erase characteristics. The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at -8 V/1 ms, and the ten-year memory window is extrapolated to be 4.41 V. This is attributed to shallow traps in p-SnO and deep traps in n-SnO₂, and the formation of a built-in electric field in the heterojunction.     

The influence of thermally assisted tunneling on the performance of charge trapping memory

We evaluate the influence of the thermally assisted tunneling (TAT) mechanism on charge trapping memory (CTM) cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, trap depth, distribution of trapped charge, gate voltage and parameters of TAT on erasing/programming speed and retention performance. TAT is an indispensable mechanism in CTM that can increase the detrapping probability of trapped charge. Our results reveal that the TAT effect causes the sensitivity of cell performance to temperature and it could affect the operational speed, especially for the erasing operation. The results show that the retention performance degrades compared with when the TAT mechanism is ignored.     

Study of anti-clockwise bipolar resistive switching in Ag/NiO/ITO heterojunction assembly

The anti-clockwise bipolar resistive switching in Ag/NiO/ITO (Indium–Tin–Oxide) heterojunctional thin film assembly is investigated. A sequential voltage sweep in 0 → V _max → 0 → ?V _min → 0 order shows intrinsic hysteresis behaviour and resistive switching in current density (J)–voltage (V) measurements at room temperature. Switching is induced by possible rupture and recovery of the conducting filaments in NiO layer mediated by oxygen ion migration and interfacial effects at NiO/ITO junction. In the high-resistance OFF-state space charge limited current passes through the filamentary path created by oxygen ion vacancies. In OFF-state, the resistive switching behaviour is attributed to trapping and detrapping processes in shallow trap states mostly consisting of oxygen vacancies. The slope of Log I vs Log V plots, in shallow trap region of space charge limited conduction is ~2 (I ∝ V ²) followed by trap-filled and trap-free conduction. In the low-resistance ON-state, the observed electrical features are governed by the ohmic conduction.     

Improved characteristics for MOHOS memory with oxygen-rich GdO as charge storage layer annealed by NH3

Characteristics of metal–oxide–high-k–oxide–silicon (MOHOS) memories with oxygen-rich or oxygen-deficient GdO as charge storage layer annealed by NH₃ or N₂ are investigated. Transmission electron microscopy, X-ray photoelectron spectroscopy and X-ray diffraction are used to analyze the cross-sectional quality, composition and crystallinity, respectively, of the stacked gate dielectric with a structure of Al/Al₂O₃/GdO/SiO₂/Si. The MOHOS capacitor with oxygen-rich GdO annealed in NH₃ exhibits a good trade-off among its memory properties: large memory window (4.8 V at ±12 V, 1 s), high programming speed (2.6 V at ±12 V/100 μs), good endurance and retention properties (window degradation of 5 % after 10⁵ program/erase cycles and charge loss of 18.6 % at 85 °C after 10 years, respectively) due to passivation of oxygen vacancies, generation of deep-level traps in the grain boundaries of the GdO layer and suppression of the interlayer between GdO and SiO₂ by the NH₃ annealing.     

Photo-induced enhancement of charge density wave current in the quasi-one-dimensional conductor TaS3

In the near vicinity of Peierls transition temperature T_P, we have measured the V-I characteristics of the quasi-one-dimensional conductor TaS₃ under dark and photo-irradiation conditions. It is found that a significant enhancement of CDW current occurs only around the threshold voltage V_t under photo-irradiation. This effect can be interpreted as a result of screening of pinning potential for CDW condensate by photo-excited quasi-particles (QP's). Further the distribution of pinning potential intensity is reflected in the behavior of V-I characteristics near V_t. Our finding suggests that the strength of pinning potential can be controlled by the photo-excited QP's in quasi-1D conductors.     

Structural and electrical properties of a high-k SmAlO3 charge trapping flash memory

In this study, we proposed the Al/Al₂O₃/SmAlO₃/SiO₂/Si flash memory devices using high-k SmAlO₃ film as a charge trapping layer and high-k Al₂O₃ film as a blocking layer. The structural and morphological features of these films were explored by X-ray diffraction, X-ray photoelectron spectroscopic and atomic force microscopy. The SmAlO₃ flash memory devices annealed at 800 °C showed excellent electrical properties, such as a large memory window of ～2.61 V (measured at a sweep voltage range of ±5 V) and a small charge loss of ～7.1% (measured time up to 10⁴ s). In addition, the charge trap centroid and charge trap density were extracted by constant current stress method.