LDC-CNTFET: A carbon nanotube field effect transistor with linear doping profile channel

In this paper, a novel carbon nanotube field effect transistor with linear doping profile channel (LDC-CNTFET) is presented. The channel impurity concentration of the proposed structure is at maximum level at source side and linearly decreases toward zero at drain side. The simulation results show that the leakage current, on-off current ratio, subthreshold swing, drain induced barrier lowering, and voltage gain of the proposed structure improve in comparison with conventional CNTFET. Also, due to spreading the impurity throughout the channel region, the proposed structure has superior performance compared with a single halo CNTFET structure with equal saturation current. Design considerations show that the proposed structure enhances the device performance all over a wide range of channel lengths.     

Novel carbon nanotube field effect transistor with graded double halo channel

A novel carbon nanotube field effect transistor with symmetric graded double halo channel (GDH–CNTFET) is presented for suppressing band to band tunneling and improving the device performance. GDH structure includes two symmetric graded haloes which are broadened throughout the channel. The doping concentration of GDH channel is at maximum level at drain/source side and is reduced gradually toward zero at the middle of channel. The doping distribution at source side of channel reduces the drain induced barrier lowering (DIBL) and the drain side suppresses the band to band tunneling effect. In addition, broadening the doping throughout the channel increases the recombination of electrons and holes and acts as an additional factor for improving the band to band tunneling. Simulation results show that applying this structure on CNTFET enhances the device performance. In comparison with double halo structure with equal saturation current, the proposed GDH structure shows better characteristics and short channel parameters. Furthermore, the delay and power delay product (PDP) analysis versus on/off current ratio shows the efficiency of the proposed GDH structure.     

非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET的解析模型

为抑制短沟道效应和热载流子效应, 提出了一种非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET新结构. 通过在圆柱坐标系中精确求解三段连续的泊松方程, 推导出新结构的沟道静电势、阈值电压以及亚阈值电流的解析模型. 结果表明, 新结构可有效抑制短沟道效应和热载流子效应, 并具有较小的关态电流. 此外, 分析还表明栅交叠区的掺杂浓度对器件的亚阈值电流几乎没有影响, 而栅电极功函数对亚阈值电流的影响较大. 解析模型结果和三维数值仿真工具ISE所得结果高度符合.     

Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

An analytical model for subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs is presented in this paper. Both the drift and diffusion components of current densities are considered for the modeling of subthreshold current. Virtual cathode concept of DG MOSFETs is utilized to model the subthreshold swing of TM-DG MOSFETs. The effect of different length ratios of the three channel regions under three different gate materials of device on the subthreshold current and subthreshold swing of the short-channel TM-DG MOSFETs have been discussed. The dependencies of subthreshold current and subthreshold swing on various device parameters have been studied. The simulation data obtained by using the commercially available 2D device simulation software ATLAS™ has been used to validate the present model.     

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.     

室温下溅射法制备高迁移率氧化锌薄膜晶体管

为降低氧化锌薄膜晶体管(ZnO TFT)的工作电压,提高迁移率,采用磁控溅射法在氧化铟锡(ITO)导电玻璃基底上室温下依次沉积NbLaO栅介质层和ZnO半导体有源层,制备出ZnO TFT,对器件的电特性进行了表征。该ZnO TFT呈现出优异的器件性能:当栅电压为5 V、漏源电压为10 V时,器件的饱和漏电流高达2.2 m A;有效场效应饱和迁移率高达107 cm~2/(V·s),是目前所报道的室温下溅射法制备ZnO TFT的最高值,亚阈值摆幅为0.28 V/decade,开关电流比大于107。利用原子力显微镜(AFM)对NbLaO和ZnO薄膜的表面形貌进行了分析,分析了器件的低频噪声特性,对器件呈现高迁移率、低亚阈值摆幅以及迟滞现象的机理进行了讨论。     

高k栅介质GeOI金属氧化物半导体场效应管阈值电压和亚阈斜率模型及其器件结构设计

通过求解沟道与埋氧层的二维泊松方程,同时考虑垂直沟道与埋氧层方向的二阶效应,建立了高κ栅介质GeOI金属氧化物半导体场效应管(MOSFET)的阈值电压和亚阈斜率解析模型,研究了器件主要结构参数对器件阈值特性、亚阈特性、短沟道效应、漏极感应势垒降低效应及衬偏效应的影响,提出了优化器件性能的结构参数设计原则及取值范围,模拟结果与TCAD仿真结果符合较好,证实了模型的正确性与实用性。     

A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs

In this paper, a new nanoscale graded channel gate stack (GCGS) double-gate (DG) MOSFET structure and its 2-D analytical model have been proposed, investigated and expected to suppress the short-channel-effects (SCEs) and improve the subthreshold performances for nanoelectronics applications. The model predicts a shift, increasing potential barrier, in the surface potential profile along the channel, which ensures a reduced threshold voltage roll-off and DIBL effects. In the proposed structure, the subthreshold current and subthreshold swing characteristics are greatly improved in comparison with the conventional DG MOSFETs. The developed approaches are verified and validated by the good agreement found with the numerical simulation. (GCGS) DG MOSFET can alleviate the critical problem and further improve the immunity of SCEs of CMOS-based devices in the nanoscale regime.     

纳米体硅鳍形场效应晶体管单粒子瞬态中的源漏导通现象

体硅鳍形场效应晶体管(FinFET)是晶体管尺寸缩小到30 nm以下应用最多的结构,其单粒子瞬态产生机理值得关注.利用脉冲激光单粒子效应模拟平台开展了栅长为30, 40, 60, 100 nm Fin FET器件的单粒子瞬态实验,研究FinFET器件单粒子瞬态电流脉冲波形随栅长变化情况;利用计算机辅助设计(technology computer-aided design, TCAD)软件仿真比较电流脉冲产生过程中器件内部电子浓度和电势变化,研究漏电流脉冲波形产生的物理机理.研究表明,不同栅长Fin FET器件瞬态电流脉冲尾部都存在明显的平台区,且平台区电流值随着栅长变短而增大;入射激光在器件沟道区下方体区产生高浓度电子将源漏导通产生导通电流,而源漏导通升高了体区电势,抑制体区高浓度电子扩散,使得导通状态维持时间长,形成平台区电流;尾部平台区由于持续时间长,收集电荷量大,会严重影响器件工作状态和性能.研究结论为纳米Fin FET器件抗辐射加固提供理论支撑.     

Novel attributes in the performance and scaling effects of carbon nanotube field-effect transistors with halo doping

In this paper, we performed a comprehensive scaling study of a carbon nanotube field-effect transistor (CNTFET) with halo doping (HD) using self-consistent and atomistic scale simulations. Our simulation results demonstrate that drain induced barrier lowering (DIBL) diminishes in the HD-CNTFET due to a step in the potential of the CNT at the interface of p-doped and undoped regions in the channel. Also, the hot carrier effect minimizes with reduction of the peak of the electric field at the drain side of the HD-CNTFET. Moreover, the features of the HD-CNTFET can be controlled by the length and concentration engineering of the HD region. Leakage current, on–off current ratio and subthreshold swing improve with an increase of the length and concentration of the HD region, due to the increment of the threshold voltage and the barrier height of the p–n junction near the source. Therefore, this work can provide an incentive for further experimental exploration.     

An oxide/silicon core/shell nanowire metal-oxide semiconductor field-effect transistor

This paper studies an oxide/silicon core/shell nanowire MOSFET(OS-CSNM).Through three-dimensional device simulations,we have demonstrated that the OS-CSNM has a lower leakage current and higher I on /I off ratio after introducing the oxide core into a traditional nanowire MOSFET(TNM).The oxide/silicon OS-CSNM structure suppresses threshold voltage roll-off,drain induced barrier lowering and subthreshold swing degradation.Smaller intrinsic device delay is also observed in OS-CSNM in comparison with that of TNM.     

Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs

The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET. Specifically, metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NC FinFETs are compared, in order to figure out the effect of the internal metal layer on the GIDL effect. To analyze the impact of the polarization gradient on the GIDL effect in NC FinFET, a polarization gradient coefficient is varied. For MFMIS, the polarization gradient doesn't significantly affect the device performance. The subthreshold swing improves but the GIDL effect deteriorates because of the “uniform” NC effect in channel region. For MFIS, the device performance is explicitly affected by the polarization gradient. Smaller polarization gradients result in non-uniform NC effect in channel region, resulting in severe GIDL effects. On the other hand, higher polarization gradients alleviate GIDL effects.     

Excellent-Performance AlGaN/GaN Fin-MOSHEMTs with Self-Aligned Al_2O_3Gate Dielectric

AlGaN/GaN fin-shaped metal-oxide-semiconductor high-electron-mobility transistors(fin-MOSHEMTs) with different fin widths(300nm and lOOnm) on sapphire substrates are fabricated and characterized.High-quality self-aligned Al_2O_3 gate dielectric underneath an 80-nm T-shaped gate is employed by aluminum self-oxidation,which induces 4 orders of magnitude reduction in the gate leakage current.Compared with conventional planar MOSHEMTs,short channel effects of the fabricated fin-MOSHEMTs are significantly suppressed due to the trigate structure,and excellent dc characteristics are obtained,such as extremely Bat output curves,smaller drain induced barrier lower,smaller subthreshold swing,more positive threshold voltage,higher transconductance and higher breakdown voltage.     

基于氧化铟锡的无结低电压薄膜晶体管

在室温下制备了基于氧化铟锡(ITO)的底栅结构无结薄膜晶体管. 源漏电极和沟道层都是同样的ITO薄膜材料,没有形成传统的源极结和漏极结, 因而极大的简化了制备流程,降低了工艺成本.使用具有大电容的双电荷层SiO₂作为栅介质, 发现当ITO沟道层的厚度降到约20 nm时, 器件的栅极电压可以很好的调控源漏电流. 这些无结薄膜晶体管具有良好的器件性能: 低工作电压(1.5 V), 小亚阈值摆幅(0.13 V/dec)、 高迁移率(21.56 cm²/V·s)和大开关电流比(1.3× 10⁶). 这些器件即使直接在大气环境中放置4个月, 器件性能也没有明显恶化:亚阈值摆幅保持为0.13 V/dec,迁移率略微下降至18.99 cm²/V·s,开关电流比依然大于10⁶.这种工作电压低、工艺简单、 性能稳定的无结低电压薄膜晶体管非常有希望应用于低能耗便携式电子产品以及新型传感器领域.     

Nanoscale SiGe-on-insulator (SGOI) MOSFET with graded doping channel for improving leakage current and hot-carrier degradation

A novel graded doping profile, for the first time is introduced for reliability improvement and leakage current reduction. The proposed structure is called graded doping channel SiGe-on-insulator (GDC-SGOI). The key idea in this work is to modify the electric field and band energy with novel doping distribution in the channel for improving leakage current and hot electron. Using two-dimensional two-carrier simulation we demonstrate that the GDC-SGOI shows lower electron temperature near the drain region in the channel in comparison with the conventional SGOI (C-SGOI) with uniform doping. On the other hand, short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement leads to leakage current reduction. DIBL decrement and less dependence of the threshold voltage and DIBL on channel length variation in the GDC-SGOI structure show SCEs suppression. Furthermore the on-off current ratio (I_on/I_off) in the GDC-SGOI is higher than that achieved from the C-SGOI. Therefore, the results show that the GDC-SGOI structure especially in low power and device reliability has excellent performance in comparison with the C-SGOI.     

双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

Subthreshold swing characteristics of nanowire tunneling FETs with variation in gate coverage and channel diameter

In this study, we demonstrate the simulated subthreshold swing (SS) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30% to 100%. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS. Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100% exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼10¹³, and an on-current of ∼10⁻⁵ A/μm.     

Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I_on), off-current (I_off), subthreshold swing (S), and I_on/I_off ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (f_T) and maximum oscillation frequency (f_max) on gate–drain capacitance (C_gd) with the underlapping were investigated as the gate length (L_gate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.     

A low subthreshold swing tunneling field effect transistor for next generation low power CMOS applications

We propose a low subthreshold swing transistor architecture called Negative Capacitance Single Gate Silicon-On-Insulator Tunneling Field Effect Transistor (NC-SG-SOI-TFET) and present an analytical model to characterize its performance. Electrostatic potential distribution and electric field intensity in the channel region are obtained by solving the Poisson equation, and the drain current is calculated using the band-to-band carrier generation rate. An additional layer of ferroelectric oxide is used to obtain the negative capacitance. Effect of ferroelectric oxide is incorporated using one-dimensional Landau formalism. Through two dimensional theoretical analysis, we show that the proposed device has superior performance over traditional TFETs in terms of subthreshold swing and short channel effects. For example, a subthreshold swing of 11.82 mV/decade and operating voltage of 0.65 V for a drain current of 10⁻⁸ A/µm have been obtained. The physics behind the improved performance is discussed based on the presented model. The analytical model would also be instrumental in designing and optimizing such devices avoiding complexities and cost of numerical models.     

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor(MOSFET) are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.