Opposite-channel-based injection of hot-carriers in SOI MOSFET's:physics and applications

An extensive study of the recently observed opposite-channel-based injection (OCBI) of hot-carriers in SOI MOSFET's is carried out by PISCES numerical calculations. The study reveals similar patterns of injection for partially-depleted (PD) and fully-depleted (FD) devices, although there are significant quantitative differences. Important differences also exist when stressing the device with the body floating versus body grounded. The results demonstrate that when stressing one channel, carriers can and are injected into the opposite gate. The results also demonstrate that under appropriate bias conditions pure electron/hole injection takes place, and establish these conditions. The practical significance of this ability to inject only electrons or only holes in any desired sequence is illustrated by exploiting it to investigate the time-power law of interface state generation and to design a SOI EEPROM cell with a back channel based erasing scheme     

Time-dependent snapback in thin-film SOI MOSFET's

During pulsed stressing of SOI MOSFETs for ESD characterization, the turn-on voltage of the parasitic bipolar transistor was observed to be a function of the stress pulse-width. This observation can be understood in terms of a capacitive charging model. The theory behind this time-dependent snapback is presented in this letter along with the experimental results. Comparisons with bulk-Si devices indicate that this phenomenon is specific to SOI and is a manifestation of the floating body effect     

Transient pass-transistor leakage current in SOI MOSFET's

This paper reports an accurate method of measuring the anomalous leakage current in pass-gate MOSFET's unique to SOI devices. A high-speed measurement setup is used to provide experimental results, and to quantify the magnitude of leakage. Particularly, great care is taken to measure only the device leakage current and not the currents due to parasitic capacitances. Systematic influences of different factors such as temperature, bias, device history, and device structure on this leakage current are experimentally established,     

Subthreshold kinks in fully depleted SOI MOSFET's

Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS     

Scaling theory for double-gate SOI MOSFET's

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t_si; gate oxide thickness t_ox) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 μm while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator     

Subthreshold slope of thin-film SOI MOSFET's

Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films. Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel. For comparison, the subthreshold slope of transistors made in thicker films is also reported.     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

Moderate inversion in SOI MOSFET's with grain boundaries

Our previous model for the effects of grain boundaries on the strong-inversion (linear region) conductance of silicon-on-insulator (SOI) MOSFET's is extended to account for moderate inversion. The extension, which is supported by measurements of laser-recrystallized devices, predicts a nearly exponential dependence for the conductance on the (front) gate voltage that is controlled by the grain boundaries.     

Numerical analysis of switching characteristics in SOI MOSFET's

The paper presents an analysis of switching characteristics in SOI MOSFET's. By using a two-carrier and two-dimensional transient SOI simulator, calculated waveforms having good agreement with experimental results are obtained. Further analysis revealed the mechanism of switching characteristics. The motion of majority carriers features the switching characteristics for SOI devices in both turn-on and turn-off stages, although the current overshooting time and the substrate potential recovery time are strongly affected by bias conditions. The magnitude of drain current overshoot in the turn-on stage also proved to be a function of substrate impurity concentration.     

Electron mobility behavior in extremely thin SOI MOSFET's

Extremely thin-film SOI MOSFET's with silicon film thickness down to 8 nm have been fabricated without inducing serious source/drain series resistance by employing a gate recessed structure. The influence of extremely thin silicon film on the electron mobility has been experimentally studied. The results show an abrupt mobility decrease in the device with less than 10 nm silicon film thickness. The measured mobility versus effective field below 10 nm silicon film thickness shows that a different scattering mechanism is involved in carrier conduction in 10 nm t_si region. The reasons for the mobility decrease have been examined from a device simulation and measurements     

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E_m). Experimental results using SOI MOSFET's with body contacts indicate that E_m is just a weak function of thin-film SOI thickness (T_si and that E_m can be significantly lower than in a bulk device with drain junction depth (X _j) comparable to SOI's T_si. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I_G) of studying E_m in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought     

Surface potential at threshold in thin-film SOI MOSFET's

The usual condition for threshold in bulk MOSFETs, of equal rates of change with gate voltage of the inversion and bulk charges, is suitably modified to describe threshold in fully depleted SOI MOSFETs. Using this modified condition the value of the surface potential at threshold in fully depleted transistors is obtained analytically in terms of device dimensions, film doping level, and applied voltages. The results are in excellent agreement with one-dimensional numerical simulations, and it is shown that the surface potential at threshold may differ significantly from 2φ_F, the value conventionally assumed     

Degradation in thin-film SOI MOSFET's caused by single-transistorlatch

The measurement of anomalous hot-carrier damage in thin-film n-channel SOI MOSFETs is reported. Due to the presence of a parasitic bipolar transistor between the source and drain, the minimum drain voltage for breakdown in these devices occurs when the device is biased in subthreshold. Using charge-pumping measurements, it is shown that if the device is biased in this regime, where single-transistor latch occurs, hot holes are injected into the gate oxide near the drain. Consequently, the maximum allowable drain voltage for these devices is governed by the parasitic bipolar properties of the SOI MOSFET     

Mobility-field behavior of fully depleted SOI MOSFET's

This work reports measured effective mobility vs. effective vertical electric field and the accompanying experimental method of extraction for the fully depleted (FD) SOI MOSFET. The effective channel mobility vs. effective vertical electric field behavior was investigated as a function of the SOI film doping concentration, the SOI back-gate bias, and the SOI film thickness. The validity of using the approximation, Q_i=C_ox(V_GS-V_TH), for the inversion charge density in FD SOI is examined and experimentally confirmed     

Transconductance of Silicon-on-insulator (SOI) MOSFET's

Transconductance of n-channel Silicon-on-Insulator (SOI) MOSFET's has been measured with backside gate (substrate) bias as a parameter. For negative values of the backside gate bias, transconductance of SOI transistors is similar to that of bulk devices. On the other hand, transconductance exhibits an unusual behavior when backside gate is positively biased. This is caused by mutual influence between the front-and the backside gate-related depletion zones. Modeling of transconductance using numerical solution of Poisson's equation show good agreement with experimental results.     

Switch-off behavior of floating-body PD SOI MOSFET's

In this work, we report a detailed study of the switch-off transients of the drain current in floating-body partially depleted (PD) SOI MOSFETs. When operated in the kink region and at frequency in the MHz range, floating body effects improve the current capability of these devices. However, we point out a serious drawback, that has been previously overlooked: the same effects lead to orders of magnitude increase of the off-state leakage current calling for a trade-off between speed and power dissipation     

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V _G-V_T values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1-μm range     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

An analytical model for snapback in n-channel SOI MOSFET's

An analytical snapback model for n-channel silicon-on-insulator (SOI) transistors with body either tied to the source or floating is been presented. The snapback is modeled as a nonlinear feedback system leading to negative transconductances from which the jump in current can occur at the point of instability. The crux of this model is based on the strong dependence of the transistor threshold voltage on the body potential when the body potential is above the transistor surface potential at strong inversion. No parasitic bipolar action is invoked to account for the snapback phenomena. The model correctly predicts the occurrence of hysteresis/latch phenomena and the conditions under which the current jump occurs despite some gross approximations in the electric field and the injection level. Results obtained from this model show good agreement with experimental data measured from SIMOX devices fabricated on 0.3-μm epi film     

Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion

A simple analytic model for the steady-state current-voltage characteristics of strongly inverted silicon-on-insulator (SOI) MOSFET's is developed. The model, simplified by a key approximation that the inversion charge density is described well by a linear function of the Surface potential, clearly shows the dependence of the drain current on the device parameters and on the terminal voltages, including the back-gate (substrate) bias. The analysis is supported by measurements of current-voltage characteristics of thin-film (laser-recrystallized) SOI MOSFET's. The dependence of carrier mobility on the terminal voltages, especially the back-gate bias, is analyzed and shown to underlie discrepancies between the theoretical (constant mobility) and experimental results at high gate voltages. The mobility dependence on the back-gate bias enhances the strong influence of the back gate on the drain current, especially when the device is saturated.