Current-mode CMOS multiple-valued logic circuits

Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described     

A novel multiple-valued logic gate using resonant tunneling devices

We demonstrate a novel multiple-valued logic (MVL) gate using series-connected resonant tunneling devices. Logic operation is based on the control of the switching sequence of these devices through the modulation of their peak currents by the input signal. We obtain the literal function, one of fundamental MVL functions, by integrating three InGaAs-based resonant-tunneling diodes with two HEMT's on an InP substrate. The gate configuration is greatly simplified compared with a conventional literal gate employing CMOS circuits     

Higher radix linear sequential circuit implementation via hybrid U and JK multiple-valued logic primitives

The implementation of a 2-digit modulo-3 linear sequential circuit (LSC) is presented, together with its associated state diagram. Two multiple valued logic (MVL) primitives are identified as suitable building blocks for the realisation of the three basic elements required for higher radix (>2) LSC hardware. Specifically, the hybrid MVL combinational U-gate and the MVL sequential JK flipflop sequencer are identified as vehicles for the implementation of modulo-radix scalars, adders and delayers.<>     

Resonant tunneling devices with multiple negative differential resistance and demonstration of a three-state memory cell for multiple-valued logic applications

A new resonant-tunneling (RT) functional device with two peaks in the current-voltage (I-V) characteristic has been demonstrated. Contrary to conventional RT devices, the peaks are obtained using a single resonance of the quantum well. The peak's separation is voltage tunable and the peak currents are nearly equal, which is important for a variety of device applications. Using a single device, a three-state memory cell has been implemented.     

Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices

This paper proposes an analog CMOS circuit that implements a central pattern generator (CPG) for locomotion control in a quadruped walking robot. Our circuit is based on an affine transformation of a reaction-diffusion cellular neural network (CNN), and uses differential pairs with multiple-input floating-gate (MIFG) MOS transistors to implement both the nonlinearity and summation of CNN cells. As a result, the circuit operates in voltage mode, and thus it is expected to reduce power consumption. Due to good matching accuracy of devices, the circuit generates stable rhythmic patterns for robot locomotion control. From experimental results on fabricated chip using a standard CMOS 1.5-/spl mu/m process, we show that the chip yields the desired results; i.e., stable rhythmic pattern generation and low power consumption.     

High-performance current-mode CMOS simultaneous implementation of window-literal operations for multi-valued logic

A new current-mode CMOS circuit for simultaneous implementation of literal and complementary literal operations is presented. It is shown that the proposed circuit exhibits superior performance compared to its previous counterparts in terms of speed power dissipation and robustness with much smaller area. These advantages make the circuit a very useful design block for multivalued logic function realisations.     

基于标准CMOS工艺制作的MOS-NDR柔性逻辑电路

本文利用0.35um标准CMOS工艺实现了一种由4个nMOSFET构成的MOS型负阻器件。这种负阻器件的I-V特性与传统的化合物材料构成的共振隧穿二极管（RTD）的特性类似,而且可以通过第三端来调制其I-V特性。基于这种MOS型负阻器件,本文实现了一种通过调节阈值电压来实现与非门（NAND）到或非门（NOR）转变的柔性逻辑电路。此种电路所用器件较少,而且由于使用标准IC的设计和工艺流程,制作工艺大大简化。     

A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metaloxide-semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 μm CMOS technology.This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current-voltage characteristics.At the same time it can realize a modulation effect by the third terminal.Based on the MOS-NDR transistor,a flexible logic circuit is realized in this work,which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor.It turns out that MOSNDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.     

基于CMOS的机器人视觉系统设计

针对机器人系统任务的特点,设计了一种单目视觉系统。采用CMOS图像传感器,通过CPLD形成控制时序,搭建了30万像素分辨力的硬件系统。基于简化的HSI颜色模型,并采用抽样方法,实现了对象状态的判断;系统采用高性能DSP器件,在进行图像处理的同时实施机器人的运动控制。系统软件算法在Matlab下进行了仿真并移植于DSP。实验结果表明,该系统实现了特定对象的状态判别功能,并具有良好的实时性。     

Design and implementation of a 5×5 trits multiplier in aquasi-adiabatic ternary CMOS logic

Adiabatic switching is a technique to design low-power digital IC's. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is presented, and to validate its performance, a 5×5 ternary digit multiplier is designed and implemented in a 0.7-μm CMOS technology. Results show a satisfactory power saving with respect to conventional and other quasi-adiabatic binary multipliers, and a decrease of the area needed with respect to a fully adiabatic binary one     

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.     

基于FPGA的PCIe接口逻辑设计与实现

为了提升高速串行计算机扩展总线标准(PCIe)总线互联设备在高速通信过程中的系统性能,减少对中央处理器(CPU)资源的占用,基于Kintex-7系列现场可编程逻辑门阵列(FPGA)平台进行总线主控式直接存储访问(DMA)设计,通过PCIe接口实现了主机设备(PC)与FPGA设备之间的高性能数据传输。同时,基于Root Port仿真平台设计DMA读写测试用例,仿真结果验证PCIe接口逻辑的正确性。通过连接上位机和配置驱动进行实际传输速率测试,结果表明,DMA写速率最高可达1 620 MB/s,DMA读速率最高可达1 427 MB/s,带宽最大值能够达到PCIe接口理论带宽值的84%。设计方案成本低,可靠性高,能够满足高性能、低延时的数据采集要求。     

NCMOS: a high performance CMOS logic

CMOS has been the mainstay technology for VLSI design for the last several years. However, recently, BiCMOS technology has been proposed for speed critical applications. In this paper we propose a new circuit structure called NCMOS, which employs a low Vt NMOS transistor in place of the bipolar transistor, and provides significantly higher speed than a conventional CMOS design. This is realized at the cost of only one extra masking step, compared to 4-5 extra masks for a full BiCMOS process     

Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach

We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON–OFF transitions with high voltage-gains (e.g., ΔV_OUT/ΔV_IN up to ～45) and symmetric pull-up and pull-down characteristics. The matching of the drive currents of n- and p-MOSFETs is achieved using different number of nanowire channels for N- and P-MOS transistors. The inverter maintains its good transfer characteristics and noise margins for wide range of V_DD tested down to 0.2 V. The detailed experimental characterization is discussed along with the electrical characteristics of the individual transistors comprising the inverter. The performances of the inverters are discussed vis-à-vis those reported in the literature using advanced non-classical device architectures such as FinFETs. The integration potential of GAA Si-nanowire transistors to realize CMOS circuit functionality using top-down approach is thus demonstrated.     

基于CMOS的电子传感接收电路的设计与实现

当前电子传感接收电路具有能耗高、性能参数不符合要求的弊端。为此,设计一种新的基于CMOS的电子传感接收电路,并介绍了电子传感接收电路设计方案。依据设计方案,选用源级负反馈电感匹配结构对低噪声放大器的基本电路结构进行设计;为达到性能指标和降低功耗,混频器电路结构选用无源双平衡混频器结构;为了降低整个电子传感接收电路的能耗,令无源双平衡混频器的开关MOS管在无电流偏置的情况下运行。给出了复数滤波器设计的基本思想,通过反馈系统对编程增益放大器的增益进行管理,实现可编程放大器的设计。实验结果表明,所设计电路性能符合设计要求。     

Current sensing differential logic: a CMOS logic for highreliability and flexibility

In this paper, we present a highly reliable and flexible CMOS differential logic called current sensing differential logic (CSDL). This CSDL eliminates the timing constraints between the enable signal and input signals, which cause difficulties in design with conventional differential logic families, by employing a simple clocking scheme. The power-delay product of CSDL is also reduced by using a swing suppression technique. To verify the reliability and the applicability of the proposed CSDL in large very large-scale-integration systems, a 64-bit carry-lookahead adder has been fabricated in a 0.6 μm CMOS technology. Experimental results show that the critical path delay is 3.5 ns with a power consumption of 27 mW at 50 MHz     

消息基VXI总线接口逻辑的模块化实现

VXI总线是一种在自动测试领域及其他多机互连系统中广泛应用的消息总线协议。文中分析了VXI总线协议的特点,根据该协议提供的通讯规范的可裁剪特征提出了模块化的VXI总线接口逻辑实现方法。并以此为基础在FPGA中实现了模块化的消息基VXI总线接口逻辑。通过模块化设计大大提高了设计的可继承性。为检验设计的可靠性和有效性,给出了FPGA设计生成的模拟时序,并将该设计应用于一种多DSP实时图像处理系统,使之能满足系统资源管理和各模块问的简单消息传递的需要。最后给出了实际测量的总线时序图,结果表明提出的设计方法和实现使VXI接口逻辑在模块化设计的同时也实现了协议所提供的总线带宽。     

Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS

Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. This paper provides comprehensive analyses on the impacts of NBTI and PBTI on wide fan-in domino gates with high-k metal-gate devices. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG) are analyzed in the presence of NBTI/PBTI degradation. It has been shown that the main concern is the degradation impact on delay which can increase up to 16.2% in a lifetime of 3 years. We have also proposed a degradation tolerant technique to compensate for the NBTI/PBTI-induced delay degradation in domino gates with a negligible impact on UNG and power.     

Novel circuit techniques for zero-power 25-ns CMOS erasable programmable logic devices (EPLDs)

A family of CMOS erasable programmable logic devices (EPLDs) is described with emphasis on the state-of-the-art chip architecture and circuit design techniques. The main features of this family of EPLDs include zero standby power, high-speed operation, flip-flop reconfigurability, small chip size, and high reliability. A novel input-transition-detection circuit allows the chip to consume no power during standby and yet wakes the chip up with minimum delay. Basic architectural differences between EPLDs and EPROM are discussed that require extra design considerations to achieve an optimal speed path through the array. A direct-drive technique is used in the transistor-transistor logic buffer and flip-flop circuits to improve speed, layout area, and chip organization.     

Behavior of a radiation-immune CMOS logic family under resistiveshorts

Previous researchers had developed a special family of CMOS logic circuits which uses additional feedback transistors to provide immunity to radiation-induced errors for space-borne electronics. It was originally speculated that these transistors, representing a form of redundancy, might provide additional benefits, such as greater tolerance of manufacturing defects. Instead, the authors work shows that the redundant transistors, because of the way in which they are used, increase the sensitivity of the circuitry to manufacturing defects which manifest themselves as resistive transistor shorts, such faults cause: (1) logic errors at the affected gate output; and (2) an increase in the signal transition delay. Furthermore, these transistors lead to higher levels of quiescent supply current, making the circuits more difficult to test using quiescent current (I_DDQ) testing