A super-junction SOI-LDMOS with low resistance electron channel

A novel super-junction LDMOS with low resistance channel(LRC), named LRC-LDMOS based on the silicon-oninsulator(SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance(Ron,sp) in forward conduction. The charge compensation between the LRC, N-pillar,and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift,thus the breakdown voltage(BV) is enhanced in reverse blocking. The three-dimensional(3 D) simulation results show that the BV and R_(on,sp) of the device can reach 253 V and 15.5 mΩ·cm~2, respectively, and the Baliga's figure of merit(FOM = BV~2/R_(on,sp)) of 4.1 MW/cm~2 is achieved, breaking through the silicon limit.     

Modeling of high permittivity insulator structure with interface charge by charge compensation

An analytical model of the power metal–oxide–semiconductor field-effect transistor(MOSFET)with high permittivity insulator structure(HKMOS)with interface charge is established based on superposition and developed for optimization by charge compensation.In light of charge compensation,the disturbance aroused by interface charge is efficiently compromised by introducing extra charge for maximizing breakdown voltage(BV)and minimizing specific ON-resistance(R_on,sp).From this optimization method,it is very efficient to obtain the design parameters to overcome the difficulty in implementing the R_on,sp–BV trade-off for quick design.The analytical results prove that in the HKMOS with positive or negative interface charge at a given length of drift region,the extraction of the parameters is qualitatively and quantitatively optimized for trading off BV and Ron,sp with JFET effect taken into account.     

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness

A novel terminal-optimized triple RESURF LDMOS(TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolarCMOS-DMOS(BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage(BV) and electrostatic discharge(ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse(TLP) tests,direct current(DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance(R_(on,sp)) of 6.99 ?·mm~2.Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.     

具有p-GaN岛状埋层耐压结构的横向AlGaN/GaN高电子迁移率晶体管

GaN基高电子迁移率晶体管(HEMT)相对较低的击穿电压严重限制了其大功率应用.为了进一步改善器件的击穿特性,通过在n-GaN外延缓冲层中引入六个等间距p-GaN岛掩埋缓冲层(PIBL)构成p-n结,提出一种基于p-GaN埋层结构的新型高耐压AlGaN/GaN HEMT器件结构.Sentaurus TCAD仿真结果表明,在关态高漏极电压状态下,p-GaN埋层引入的多个反向p-n结不仅能够有效调制PIBL AlGaN/GaN HEMT的表面电场和体电场分布,而且对于缓冲层泄漏电流有一定的抑制作用,这保证了栅漏间距为10μm的PIBL HEMT能够达到超过1700 V的高击穿电压(BV),是常规结构AlGaN/GaN HEMT击穿电压(580 V)的3倍.同时,PIBL结构AlGaN/GaN HEMT的特征导通电阻仅为1.47 m?·cm~2,因此获得了高达1966 MW·cm~(-2)的品质因数(FOM=BV~2/R_(on,sp)).相比于常规的AlGaN/GaN HEMT,基于新型p-GaN埋岛结构的HEMT器件在保持较低特征导通电阻的同时具有更高的击穿电压,这使得该结构在高功率电力电子器件领域具有很好的应用前景.     

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

A uniform doping ultra-thin silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor(LDMOS)with low specific on-resistance(R_on,sp) and high breakdown voltage(BV) is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate(AG) and back-side etching(BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping(VLD) and the "hot-spot" caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.     

具有半绝缘多晶硅完全三维超结横向功率器件

为了突破传统LDMOS (lateral double-diffused MOSFET)器件击穿电压与比导通电阻的硅极限的2.5 次方关系, 降低LDMOS器件的功率损耗, 提高功率集成电路的功率驱动能力, 提出了一种具有半绝缘多晶硅SIPOS (semi-insulating poly silicon)覆盖的完全3 D-RESURF (three-dimensional reduced surface field)新型Super Junction-LDMOS结构(SIPOS SJ-LDMOS). 这种结构利用SIPOS的电场调制作用使SJ-LDMOS的表面电场分布均匀, 将器件单位长度的耐压量提高到19.4 V/μupm; 覆盖于漂移区表面的SIPOS使SJ-LDMOS沿三维方向均受到电场调制, 实现了LDMOS的完全3 D-RESURF效应, 使更高浓度的漂移区完全耗尽而达到高的击穿电压; 当器件开态工作时, 覆盖于薄场氧化层表面的SIPOS的电场作用使SJ-LDMOS的漂移区表面形成多数载流子积累, 器件比导通电阻降低. 利用器件仿真软件ISE分析获得, 当SIPOS SJ-LDMOS的击穿电压为388 V时, 比导通电阻为20.87 mΩ·cm², 相同结构参数条件下, N-buffer SJ-LDMOS的击穿电压为287 V, 比导通电阻为31.14 mΩ·cm²; 一般SJ-LDMOS 的击穿电压仅为180 V, 比导通电阻为71.82 mΩ·cm².     

高k介质电导增强SOI LDMOS机理与优化设计

本文提出一种高k介质电导增强SOI LDMOS新结构（HK CE SOI LDMOS）,并研究其机理. HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻. 借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系. 结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%–18%,同时比导通电阻降低13%–20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题. 关键词： k介质')" href="#">高k介质 绝缘体上硅 (SOI) 击穿电压 比导通电阻     

Design and simulation of AlN-based vertical Schottky barrier diodes

The key parameters of vertical AlN Schottky barrier diodes(SBDs) with variable drift layer thickness(DLT) and drift layer concentration(DLC) are investigated. The specific on-resistance(R_(on,sp)) decreased to 0.5 m? · cm~2 and the breakdown voltage(V_(BR)) decreased from 3.4 kV to 1.1 kV by changing the DLC from 10~(15) cm~(-3) to 3×10~(16) cm~(-3). The VBRincreases from 1.5 kV to 3.4 kV and the Ron,sp also increases to 12.64 m? · cm~2 by increasing DLT from 4-μm to 11-μm. The VBRenhancement results from the increase of depletion region extension. The Baliga's figure of merit(BFOM) of3.8 GW/cm~2 was obtained in the structure of 11-μm DLT and 10~(16) cm~(-3) DLC without FP. When DLT or DLC is variable,the consideration of the value of BFOM is essential. In this paper, we also present the vertical AlN SBD with a field plate(FP), which decreases the crowding of electric field in electrode edge. All the key parameters were optimized by simulating based on Silvaco-ATLAS.     

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

A new ultra-low specific on-resistance(Ron,sp) vertical double diffusion metal–oxide–semiconductor field-effect transistor(VDMOS) with continuous electron accumulation(CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration(Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp.Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS(CSJ-VDMOS)at the same high breakdown voltage(BV).     

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-$K$/low-$K$ compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-$K$ and low-$K$ layers due to the different dielectric constants of high-$K$ and low-$K$ dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p-n junction interface is suppressed due to the effects of the high-$K$ dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance ($R_{\rm on, sp}$) of 2.07 m$\Omega\cdot$cm$^{2}$ and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm$^{2}$, and a low turn-on voltage of 0.6 V.     

蓝宝石R面上ZnO薄膜的NH3掺杂研究

以NH₃为掺杂源,利用金属有机化学气相沉积(MOCVD)系统在蓝宝石R面上生长出掺氮ZnO薄膜。通过XRD,SEM测量优化了其生长参数,在610℃和在80sccm的NH₃流量下生长出了〈1120〉单一取向的ZnO薄膜。经Hall电阻率测量,得知该薄膜呈现弱p型或高电阻率,并对其光电子能谱进行了研究。     

Etching mask optimization of InAs/GaSb superlattice mid-wavelength infared 640×512 focal plane array

In this paper we focused on the mask technology of inductively coupled plasma(ICP) etching for the mesa fabrication of infrared focal plane arrays(FPA).By using the SiO_2 mask,the mesa has higher graphics transfer accuracy and creates less micro-ripples in sidewalls.Comparing the IV characterization of detectors by using two different masks,the detector using the SiO_2 hard mask has the R_0A of 9.7×10~6 Ω·cm~2,while the detector using the photoresist mask has the R_0A of3.2 × 10~2 Ω·cm~2 in 77 K.After that we focused on the method of removing the remaining SiO_2 after mesa etching.The dry ICP etching and chemical buffer oxide etcher(BOE) based on HF and NH4 F are used in this part.Detectors using BOE only have closer R_0A to that using the combining method,but it leads to gaps on mesas because of the corrosion on AlSb layer by BOE.We finally choose the combining method and fabricated the 640×512 FPA.The FPA with cutoff wavelength of 4.8 μm has the average R_0A of 6.13 × 10~9 Ω·cm~2 and the average detectivity of 4.51 × 10~9 cm·Hz~(1/2).W~(-1)at 77 K.The FPA has good uniformity with the bad dots rate of 1.21%and the noise equivalent temperature difference(NEDT) of 22.9 mK operating at 77 K.     

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

The product of the cutoff frequency and breakdown voltage( fT×BVCEO) is an important figure of merit(FOM) to characterize overall performance of heterojunction bipolar transistor(HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator(SOI) Si Ge HBT to simultaneously improve the FOM of fT×BVCEOand thermal stability is presented by using two-dimensional(2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness(TBOX) on fT, BVCEO, and the FOM of fT×BVCEOare presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEOto some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT,BVCEO, and the FOM of fT×BVCEOcan be improved by increasing SOI insulator Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEOis improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI Si Ge HBT overall performance.     

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (R_on.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in R_on.sp by 45.7% simultaneously.     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

Study on the local structure of (CrO6) complex in garnet crystals by optical and EPR spectrum

The local lattice structure distortions for YAG and YGG systems doped with Cr³⁺ have been investigated by the d³ configuration complete energy matrices which contain the Zeeman energy besides the electron–electron interaction, the trigonal crystal field as well as the spin–orbit coupling interaction. The local lattice structure parameters R and θ of (CrO₆)⁹⁻ complex are determined for Cr³⁺ in YAG and YGG systems, respectively. The calculated results show that the local lattice structures have expansion distortions, which almost tend to the same after distortions. Meanwhile, the EPR parameter D, g factors (g_||, g) and optical spectrum of these systems have been interpreted uniformly by quantitative calculation. It is shown that the effect of the orbit reduction factor k on g factors (g_||, g) cannot be ignored.     

具有纵向辅助耗尽衬底层的新型横向双扩散金属氧化物半导体场效应晶体管

为了优化横向双扩散金属氧化物半导体场效应晶体管(lateral double-diffused MOSFET,LDMOS)的击穿特性及器件性能,在传统LDMOS结构的基础上,提出了一种具有纵向辅助耗尽衬底层(assisted depletesubstrate layer,ADSL)的新型LDMOS.新加入的ADSL层使得漏端下方的纵向耗尽区大幅向衬底扩展,从而利用电场调制效应在ADSL层底部引入新的电场峰,使纵向电场得到优化,同时横向表面电场也因为电场调制效应而得到了优化.通过ISE仿真表明,当传统LDMOS与ADSL LDMOS的漂移区长度都是70μm时,击穿电压由462 V增大到897 V,提高了94%左右,并且优值也从0.55 MW/cm~2提升到1.24 MW/cm~2,提升了125%.因此,新结构ADSL LDMOS的器件性能较传统LDMOS有了极大的提升.进一步对ADSL层进行分区掺杂优化,在新结构的基础上,击穿电压在双分区时上升到938 V,三分区时为947 V.     

Analysis of frequency-dependent series resistance and interface states of In/SiO2/p-Si (MIS) structures

In this work, the investigation of the interface state density and series resistance from capacitance–voltage (C–V) and conductance–voltage (G/ω−V) characteristics in In/SiO₂/p-Si metal–insulator–semiconductor (MIS) structures with thin interfacial insulator layer have been reported. The thickness of SiO₂ film obtained from the measurement of the oxide capacitance corrected for series resistance in the strong accumulation region is 220 Å. The forward and reverse bias C–V and G/ω−V characteristics of MIS structures have been studied at the frequency range 30 kHz–1 MHz at room temperature. The frequency dispersion in capacitance and conductance can be interpreted in terms of the series resistance (R_s) and interface state density (D_it) values. Both the series resistance R_s and density of interface states D_it are strongly frequency-dependent and decrease with increasing frequency. The distribution profile of R_s–V gives a peak at low frequencies in the depletion region and disappears with increasing frequency. Experimental results show that the interfacial polarization contributes to the improvement of the dielectric properties of In/SiO₂/p-Si MIS structures. The interface state density value of In/SiO₂/p-Si MIS diode calculated at strong accumulation region is 1.11×10¹² eV⁻¹ cm⁻² at 1 MHz. It is found that the calculated value of D_it (≈10¹² eV⁻¹ cm⁻²) is not high enough to pin the Fermi level of the Si substrate disrupting the device operation.     

基于介质环形柱结构的二维光子晶体中Dirac点的实现

利用偶然简并方法在二维正方格子介质环形柱结构光子晶体中成功实现了Dirac点, 并利用平面波展开法对实现Dirac点的过程进行了研究. 研究结果表明, 对于二维正方格子介质环形柱结构光子晶体, 在一定的外径R_O范围内(0.37a<R_O<0.5a), 当Dirac点存在时(n>1.4), 介质环内径R_I与外径R_O满足一个不随介质环折射率n变化的恒定关系式. 同时, Dirac点对应的光子约化频率f随折射率n及外径R_O的增大而减小. 利用所得的关系式对特定介质环折射率n条件下能实现Dirac点的环形光子晶体进行了预判设计.     

宏观放电参数对快原子态氮(N+,Nf)的影响

采用氮直流辉光放电等离子体中快电子和重粒子(N₂⁺,N⁺,N_f)混合的蒙特卡罗方法,模拟研究了快原子态粒子(N⁺,N_f)的产生率及轰击阴极的能量分布随宏观放电参数(P,V)的变化规律.结果表明,存在一最佳放电条件,使阴极壁处粒子(N⁺,N_f)的粒子数密度大且能量高;当电压大于800V时,轰击阴极的活性粒子(N⁺,N_f),主要由N₂⁺-N₂离解过程产生,电压小于300V时,主要由e^--N₂离解过程产生,模拟结果与实验结果相符合.