Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytical model,we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET,which characterize the DIBL effect.The results show that they are significantly dependent on the drain bias,gate length as well as the thickness and doping concentration of the two channel layers.Based on this analytical model,the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

单Halo全耗尽应变Si 绝缘硅金属氧化物半导体场效应管的阈值电压解析模型

为了改善金属氧化物半导体场效应管(MOSFET) 的短沟道效应(SCE)、 漏致势垒降低(DIBL) 效应, 提高电流的驱动能力, 提出了单Halo 全耗尽应变硅绝缘体 (SOI) MOSFET 结构, 该结构结合了应变Si, 峰值掺杂Halo结构, SOI 三者的优点. 通过求解二维泊松方程, 建立了全耗尽器件表面势和阈值电压的解析模型. 模型中分析了弛豫层中的Ge组分对表面势、表面场强和阈值电压的影响, 不同漏电压对表面势的影响, Halo 掺杂对阈值电压和DIBL的影响.结果表明, 该新结构能够抑制SCE和DIBL效应, 提高载流子的输运效率. 关键词： 应变Si 阈值电压 短沟道效应 漏致势垒降低     

New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor (4H-SiC MESFET) structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications. The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one- and two-dimensional Poisson's equations. In the models, we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted. The direct-current and the alternating-current performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 μ m are calculated. The calculated results are in good agreement with the experimental data. The current is larger than that of the conventional structure. The cutoff frequency (f_T) and the maximum oscillation frequency (f_max) are 20.4 GHz and 101.6 GHz, respectively, which are higher than 7.8 GHz and 45.3 GHz of the conventional structure. Therefore, the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.     

New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor (4H-SiC MESFET) structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications.The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one-and two-dimensional Poisson’s equations.In the models,we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted.The direct-current and the alternatingcurrent performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 μm are calculated.The calculated results are in good agreement with the experimental data.The current is larger than that of the conventional structure.The cutoff frequency (fT) and the maximum oscillation frequency (f max) are 20.4 GHz and 101.6 GHz,respectively,which are higher than 7.8 GHz and 45.3 GHz of the conventional structure.Therefore,the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.     

n型金属氧化物半导体场效应晶体管噪声非高斯性研究

基于n型金属氧化物半导体场效应晶体管（nMOSFET）噪声的数涨落模型,采用高阶统计量双相干系数平方和研究了nMOSFET噪声的非高斯性.通过对nMOSFET实际测试噪声的分析,发现nMOSFET器件噪声存在非高斯性;小尺寸器件噪声的非高斯性强于大尺寸器件;在器件的强反型线性区,其非高斯性随着漏压的增加而增加.文中还通过蒙特卡罗模拟和中心极限定理理论对nMOSFET噪声的非高斯性作了深入的探讨. 关键词： 噪声 非高斯性 n型金属氧化物半导体场效应晶体管 氧化层陷阱     

A new physics-based self-heating effect model for 4H-SiC MESFETs

A new self-heating effect model for 4H-SiC MESFETs is proposed based on a combination of an analytical and a computer aided design (CAD) oriented drain current model. The circuit oriented expressions of 4H-SiC low-field electron mobility and in-complete ionization rate, which are related to temperature, are presented in this model, which are used to estimate the self-heating effect of 4H-SiC MESFETs. The verification of the present model is made, and the good agreement between simulated results and measured data of DC I-V curves with the self-heating effect is obtained.     

环栅肖特基势垒金属氧化物半导体场效应管漏致势垒降低效应研究

结合环栅肖特基势垒金属氧化物半导体场效应管(MOSFET)结构, 通过求解圆柱坐标系下的二维泊松方程得到了表面势分布, 并据此建立了适用于低漏电压下的环栅肖特基势垒NMOSFET阈值电压模型.根据计算结果, 分析了漏电压、沟道半径和沟道长度对阈值电压和漏致势垒降低的影响, 对环栅肖特基势垒MOSFET器件以及电路设计具有一定的参考价值. 关键词： 环栅肖特基势垒金属氧化物半导体场效应管 二维泊松方程 阈值电压模型 漏致势垒降低     

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

We propose a distinct approach to implement a laterally single diffused metal-oxide-semiconductor (LSMOS) FET with only one impurity doped p-n junction. In the LSMOS, a single p-n junction is first created using lateral dopant diffusion. The channel is formed in the p region of the p-n junction and the n region acts as the drift region. Two distinct metals of different work function are used to form the “n⁺” source/drain regions and “p⁺” body contact using the charge plasma concept. We demonstrate that the LSMOS is similar in performance to a laterally double diffused metal-oxide-semiconductor (LDMOS) although it has only one impurity doped p-n junction. The LSMOS exhibits a breakdown voltage of ∼50.0 V, an average ON-resistance of 48.7 mΩ-mm² and a peak transconductance of 53.6 μS/μm similar to that of a comparable LDMOS.     

阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.     

高功率微波作用下金属氧化物半导体场效应管响应

采用基于半导体漂移扩散模型的数值模拟软件对高功率微波（HPM）作用下金属氧化物半导体场效应管（MOSFET）的响应进行了数值模拟研究。对MOSFET在HPM作用下的输出特性以及器件内部响应进行了数值模拟。计算结果表明,在MOSFET栅极加载HPM后,随着注入HPM幅值的增大,会使得器件的正向电压小于开启电压,从而使得输出电流的波形发生形变。在器件内部,导电沟道靠近源极一端的电场强度最大,热量产生集中在这一区域。在脉冲正半周期时,温度峰值位于沟道源极一端,负半周期时,器件内部几乎没有电流,器件内的温度峰值在热扩散效应的影响下趋向于导电沟道中部。     

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two- dimensional Poisson’s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor (SMGFET).     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

Parameter analysis for gate metal-oxide-semiconductor structures of ion-implanted 4H silicon carbide metal-semiconductor field-effect transistors

From the theoretical analysis of the thermionic emission model of current-voltage characteristics, this paper extracts the parameters for the gate Schottky contact of two ion-implanted 4H-SiC metal-semiconductor field-effect transistors (sample A and sample B for three and four times multiple ion-implantation channel region respectively) fabricated in the experiment, including the ideality factor, the series resistance, the zero-field barrier height, the interface oxide capacitance, the interface state density distribution, the neutral level of interface states and the fixed space charge density. The methods to improve the interface of the ion-implanted Schottky contact are given at last.     

高k栅介质应变Si SOI MOSFET的阈值电压解析模型

在结合应变Si,高k栅和SOI结构三者的优点的基础上,提出了一种新型的高k栅介质应变Si全耗尽SOI MOSFET结构.通过求解二维泊松方程建立了该新结构的二维阈值电压模型,在该模型中考虑了影响阈值电压的主要参数.分析了阈值电压与弛豫层中的Ge组分、应变Si层厚度的关系.研究结果表明阈值电压随弛豫层中Ge组分的提高和应变Si层的厚度增加而降低.此外,还分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系.研究结果表明阈值电压随高k介质的介 关键词： 应变Si k栅')" href="#">高k栅 短沟道效应 漏致势垒降低     

超深亚微米互补金属氧化物半导体器件的剂量率效应

对0.18 μm互补金属氧化物半导体(CMOS)工艺的N型金属氧化物半导体场效应晶体管(NMOSFET)及静态随机存储器(SRAM)开展了不同剂量率下的电离总剂量辐照试验研究. 结果表明: 在相同累积剂量, SRAM的低剂量率辐照损伤要略大于高剂量率辐照的损伤, 并且低剂量率辐照损伤要远大于高剂量率辐照加与低剂量率辐照时间相同的室温退火后的损伤. 虽然NMOSFET 低剂量率辐照损伤略小于高剂量率辐照损伤, 但室温退火后, 高剂量率辐照损伤同样要远小于低剂量率辐照损伤. 研究结果表明0.18 μm CMOS工艺器件的辐射损伤不是时间相关效应. 利用数值模拟的方法提出了解释CMOS器件剂量率效应的理论模型.     

Model of hot-carrier induced degradation in ultra-deep sub-micrometer nMOSFET

The degradation produced by hot carrier(HC) in ultra-deep sub-micron n-channel metal oxide semiconductor field effect transistor(nMOSFET) has been analyzed in this paper. The generation of negatively charged interface states is the predominant mechanism for the ultra-deep sub-micron nMOSFET. According to our lifetime model of p-channel MOFET(pMOFET) that was reported in a previous publication, a lifetime prediction model for nMOSFET is presented and the parameters in the model are extracted. For the first time, the lifetime models of nMOFET and pMOSFET are unified. In addition, the model can precisely predict the lifetime of the ultra-deep sub-micron nMOSFET and pMOSFET.     

High energy electron radiation effect on Ni and Ti/4H-SiCSchottky barrier diode at room temperature

This paper reports that Ni and Ti/4H-SiC Schottky barrier diodes (SBDs) were fabricated and irradiated with 1~MeV electrons up to a dose of 3.43×10¹⁴~e/cm². After radiation, the Schottky barrier height φ _B of the Ni/4H-SiC SBD increased from 1.20~eV to 1.21~eV, but decreased from 0.95~eV to 0.94~eV for the Ti/4H-SiC SBD. The degradation of φ _B could be explained by interface states of changed Schottky contacts. The on-state resistance R_S of both diodes increased with the dose, which can be ascribed to the radiation defects. The reverse current of the Ni/4H-SiC SBD slightly increased, but for the Ti/4H-SiC SBD it basically remained the same. At room temperature, φ _B of the diodes recovered completely after one week, and the R_S partly recovered.     

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

The present paper proposes a new Fin Field Effect Transistor (FinFET) with an amended Channel (AC). The fin region consists of two sections; the lower part which has a rounded shape and the upper part of fin as conventional FinFETs, is cubic. The AC-FinFET devices are proven to have a lower threshold voltage roll-off, reduced DIBL, better subthreshold slope characteristics, and a better gate capacitance in comparison with the C-FinFET. Moreover, the simulation result with three-dimensional and two-carrier device simulator demonstrates an improved output characteristic of the proposed structure due to reduction of self-heating effect. Due to the rounded shape of the lower fin region and decreasing corner effects there, the heat can flow easily, and the device temperature will decrease. Also the gate control over the channel increases due to the narrow upper part of the fin. The paper, thus, attempts to show the advantages of higher performance AC-FinFET device over the conventional one, and its effect on the operation of nanoscale devices.     

HfO2基铁电场效应晶体管读写电路的单粒子翻转效应模拟

使用器件-电路仿真方法搭建了氧化铪基铁电场效应晶体管读写电路,研究了单粒子入射铁电场效应晶体管存储单元和外围灵敏放大器敏感节点后读写数据的变化情况,分析了读写数据波动的内在机制.结果表明:高能粒子入射该读写电路中的铁电存储单元漏极时,处于"0"状态的存储单元产生的电子空穴对在器件内部堆积,使得栅极的电场强度和铁电极化增大,而处于"1"状态的存储单元由于源极的电荷注入作用使得输出的瞬态脉冲电压信号有较大波动;高能粒子入射放大器灵敏节点时,产生的收集电流使处于读"0"状态的放大器开启,导致输出数据波动,但是其波动时间仅为0.4 ns,数据没有发生单粒子翻转能正常读出.两束高能粒子时间间隔0.5 ns先后作用铁电存储单元漏极,比单束高能粒子产生更大的输出数据信号波动,读写"1"状态的最终输出电压差变小.