氮化硅介质中双层纳米硅薄膜的两级电荷存储

研究镶嵌在超薄非晶氮化硅(a-SiN_x)层之间的双层纳米硅(nc-Si)的电荷存储现象.利用等离子体增强化学气相淀积(PECVD)技术在硅衬底上制备a-SiN_x/a-Si/a-SiN_x/a-Si/a-SiN_x多层薄膜结构.采用常规热退火方法使非晶硅(a-Si)层晶化，形成包含双层nc-Si的金属-氮化物-半导体(MIS)结构.通过电容电压(C-V)特性测量，观测到该结构中由于电荷存储引起的C-V回滞现象，并在室温下成功观察到载流子基于Fowler-Nordheim(F-N)隧穿注入到第一层、第二层nc-Si的两级电荷存储状态.结合电流电压(I-V)特性的测量，对电荷存储的机理进行了深入分析. 关键词： 纳米硅 氮化硅 电容电压法 电流电压法     

硅量子点中电子的荷电动力学特征

利用频率依赖电容谱的测量,对于SiO₂/硅量子点/SiO₂/硅衬底隧 穿电容中硅量子点的荷电特征进行了研究.由于量子点的极小尺寸和良好的均匀性,室温下 在强反型区成功地观察到了与单电子隧穿相关的两个电容和电导共振峰,它们分别对应于硅 衬底导带上的电子与量子点中第一与第二个基态之间直接隧穿过程.实验数据分析给出了量 子点中的库仑荷电能,并进行了讨论. 关键词： 量子点 电容谱 库仑荷电能 直接隧穿     

钙钛矿结构Pr1－xCaxMnO3薄膜中电脉冲诱导电阻值变化的理论研究

建立一个有效的三明治隧穿模型研究在Pr_1-xCa_xMnO₃薄膜中电流脉冲引起的电阻改变(EPIR)性质，发现载流子在三明治结构各区域间的隧穿概率以及在不均匀界面层的导通概率对材料的EPIR值产生重要影响.还研究了电流-电压曲线中的迟滞效应，得到的结果与近年来的文献报道一致. 关键词： 强关联电子系统 金属-氧化物界面 隧穿     

尺寸可控的纳米硅的生长模型和实验验证

基于经典热力学理论，对a-SiN_x/a-Si:H/a-SiN_x三明治结构或a-Si:H/a-SiN_x多层膜结构中纳米硅成核，以及从球形到鼓形的生长过程进行了研究. 建立了限制性晶化理论模型：在纳米硅生长过程中，由于界面能增大将导致生长停止，给出限制性晶化条件——a-Si:H子层厚度小于34 nm. 在激光晶化和常规热退火两种方法形成的a-SiN_x/nc-Si/a-SiN_x三明治结构和nc-Si/a-SiN_x多层膜结构中验证了该理论模型. 关键词： 非晶硅 纳米硅 激光辐照 结晶     

控制氧化层对双势垒纳米硅浮栅存储结构性能的影响

在等离子体增强化学气相沉积(PECVD)系统中,利用逐层淀积非晶硅(a-Si)和等离子体氧化相结合的方法制备二氧化硅(SiO₂)介质层.电容电压(C-V)和电导电压(G-V)测量结果表明：利用该方法在低温(250 ℃)条件下制备的SiO₂介质层均匀致密,其固定氧化物电荷和界面态密度分别为9×10¹¹cm^-2和2×10¹¹cm^-2·eV^-1,击穿场强达4.6 MV/cm,与热氧化形成的SiO₂介质层的性质相当.将该SiO₂介质层作为控制氧化层应用在双势垒纳米硅(nc-Si)浮栅存储结构中,通过调节控制氧化层的厚度,有效阻止栅电极与nc-Si之间的电荷交换,延长存储时间,使存储性能得到明显改善. 关键词： 等离子体氧化 二氧化硅 纳米硅 控制氧化层     

内嵌InAs量子点的δ掺杂GaAs/AlxGa1-xAs二维电子气特性分析

采用分子束外延技术对δ掺杂GaAs/Al_xGa_1-xAs二维电子气(2DEG)样品进行了生长. 在样品生长过程中, 分别改变掺杂浓度(N_d)、空间隔离层厚度(W_d) 和Al_xGa_1-xAs中Al组分(x_Al)的大小, 并在双温(300 K, 78 K)条件下对生长的样品进行了霍尔测量; 结合测试结果, 分别对N_d, W_d及x_Al与GaAs/Al_xGa_1-xAs 2DEG的载流子浓度和迁移率之间的关系规律进行了细致的分析讨论. 生长了包含有低密度InAs量子点层的δ掺杂GaAs/Al_xGa_1-xAs 2DEG 样品, 采用梯度生长法得到了不同密度的InAs量子点. 霍尔测量结果表明, 随着InAs量子点密度的增加, GaAs/Al_xGa_1-xAs 2DEG的迁移率大幅度减小, 实验中获得了密度最低为16×10⁸/cm²的InAs量子点样品. 实验结果为内嵌InAs量子点的δ掺杂GaAs/Al_xGa_1-xAs 2DEG的研究和应用提供了依据和参考. 关键词： 二维电子气 InAs量子点 载流子浓度 迁移率     

LaON/SiO2和HfON/SiO2双隧穿层MONOS存储器存储特性的比较

本文对比研究了LaON/SiO₂和HfON/SiO₂双隧穿层MONOS存储器的存储特性. 实验结果表明,LaON/SiO₂双隧穿层MONOS存储器具有较大的存储窗口,快的编程/擦除速度及好的疲劳和保持特性. 其机理在于LaON较大的介电常数有效提高了编程/擦除过程中载流子的注入效率,较小的O 扩散系数减少了界面陷阱,从而减少了保持期间存储电荷通过陷阱辅助隧穿的泄漏. 而且N的结合在界面附近形成了强的La-N,Hf-N 和O-N键,可有效降低编程/擦除循环应力对界面的损伤,使器件具有好的疲劳特性. 此外,研究了退火温度对存储特性的影响,结果表明800 ℃退火样品的存储特性比700 ℃退火的好,这是因为800 ℃时NO退火可在LaON（HfON）中引入更多的N,且能更好释放应力,使介质中缺陷减少. 关键词： MONOS 双隧穿层 LaON HfON     

GaAs间隔层厚度对InAs/GaAs量子点分子光学性质的影响

采用光致荧光发射谱(PL)和时间分辨荧光发射谱(TRPL)研究了GaAs间隔层厚度对自组装生长的双层InAs/GaAs量子点分子光学性质的影响.首先,测量低温下改变激发强度的PL谱,底层量子点和顶层量子点的PL强度比值随激发强度发生变化,表明两层量子点之间的耦合作用和层间载流子的转移随着间隔层厚度变大而变弱.接着测量改变温度的PL谱,量子点荧光光谱峰值位置(Emax)、半峰全宽及积分强度随温度发生变化,表明GaAs间隔层厚度直接影响到量子点内载流子的动力学过程和量子点发光的热淬灭过程.最后,TRPL测量发现60mL比40mL间隔层厚度样品的载流子隧穿时间有明显延长.     

基于Si-rich SiNx/N-rich SiNy多层膜结构的量子点构筑及发光特性

利用等离子体增强化学气相沉积法制备Si-rich SiN_x/N-rich SiN_y多层膜,分别使用热退火和激光辐照技术对多层膜进行退火,以构筑三维限制、尺寸可控、有序的硅纳米晶.实验结果表明,经退火后,纳米硅晶粒在Si-rich SiN_x子层内形成,其尺寸可由Si-rich SiN_x子层厚度调控.实验还发现,激光辐照技术相比于热退火能更有效地改善多层膜的微结构,提高多层膜的晶化率,以激光技术诱导晶化的Si-rich SiN_x/N-rich SiN_y多层膜作为有源层构建电致发光器件,在室温下观察到了增强的电致可见发光,并且发光效率较退火前提高了40%以上. 关键词： 氮化硅 多层膜 限制结晶 纳米晶硅     

CdSe/ZnSe异质结构中Zn1－xCdxSe量子岛(点)的显微荧光光谱和显微拉曼光谱研究

利用显微荧光和显微拉曼光谱,研究了分子束外延生长的CdSe/ZnSe异质结构中,由两种不同机理形成的两类具有不同尺寸和组分的Zn1-xCdxSe量子岛.4.2 K时的显微荧光光谱表明,当CdSe淀积厚度由1.8 ML增加到2.3ML时,Zn1-xCdxSe量子岛的激子荧光峰有166 meV的较大红移,这是量子岛尺寸改变引起的量子限制势能变化所不能完全解释的.经过对样品的显微荧光和显微拉曼光谱的对比分析,发现还存在另外两种引起量子岛荧光峰较大红移的机理：一方面是因为随着CdSe淀积厚度的增加,具有更低能态的大岛密度的增加,并逐渐取代小岛而主导Zni-xCdxSe量子岛的荧光性质;另一方面是由于CdSe/ZnSe量子结构中的两类量子岛的Cd组分浓度也会随CdSe淀积厚度的增加而增加,从而引起量子岛荧光峰的较大红移.     

Resonant Tunnelling and Storage of Electrons in Si Nanocrystals within a-SiNx/nc-Si/a-SiNx Structures

The a-SiNx/nanocrystalline silicon （nc-Si）/a-SiNx sandwiched structures with asymmetric double-barrier are fabricated in a plasma enhanced chemical vapour deposition （PECVD） system on p-type Si substrates. The nc-Si layer in thickness 5nm is fabricated from a hydrogen-diluted silane gas by the layer-by-layer deposition technique. The thicknesses of tunnel and control SiNx layers are 3nm and 20nm, respectively. Frequency-dependent capacitance spectroscopy is used to study the electron tunnelling and the storage in the sandwiched structures. Distinct frequency-dependent capacitance peaks due to electrons tunnelling into the nc-Si dots and capacitance-voltage （C - V） hysteresis characteristic due to electrons storage in the nc-Si dots are observed with the same sample. Moreover, conductance peaks have also been observed at the same voltage region by conductance-voltage （G - V） measurements. The experimental results demonstrate that electrons can be loaded onto nc-Si dots via resonant tunnelling and can be stored in our a-SiNx/nc-Si/a-SiNx structures.     

Large Storage Window in a-SiNx/nc-Si/a-SiNx Sandwiched Structure for Nanocrystalline Silicon Floating Gate Memory Application

An a-SiNx/nanocrystalline silicon [（nc-Si）/a-SiNx] sandwiched structure is fabricated in a plasma enhanced chemical vapour deposition （PECVD） system at low temperature （250℃）. The nc-Si layer is fabricated from a hydrogen-diluted silane mixture gas by using a layer-by-layer deposition technique. Atom force microscopy measurement shows that the density of nc-Si is about 2 ×10^11 cm^-2. By the pretreatment of plasma nitridation, low density of interface states and high-quality interface between the Si substrate and a-SiNs insulator layer are obtained. The density of interface state at the midgap is calculated to be 1 ×10^10 cm^-2eV^-1 from the quasistatic and high frequency C - V data. The charging and discharging property of nc-Si quantum dots is studied by capacitance-voltage （C- V） measurement at room temperature. An ultra-large hysteresis is observed in the C - V characteristics, which is attributed to storage of the electrons and holes into the nc-Si dots. The long-term charge-loss process is studied and ascribed to low density of interface states at SiNx/Si substrate.     

The charge storage of the nc—Si layer

Sandwiched structures (a-SiN_x/a-Si/a-SiN_x) have been fabricated by the plasma enhanced chemical vapour deposition technique. A Si nanocrystal (nc-Si) layer was formed by crystallization of an a-Si layer according to the constrained crystallization principle after quasi-static thermal annealing at 1100℃ for 30 min. Transmission electron microscopy (TEM) and Raman scattering spectroscopy clearly demonstrated that nc-Si grains were formed in the as-deposited a-Si layer after annealing. The density of nc-Si grains is about 10¹¹cm^-2 as shown by TEM photographs. Using capacitance－voltage (C－V) measurements we investigated the electrical characteristics of the sandwiched structures. The charge storage phenomenon of the nc-Si layer was observed from the shift of flat-band voltage (V_FB) in C－V curves at a high frequency (1 MHz). We estimated the density of nc-Si grains to be about 10¹¹cm^-2 from the shift value of V_FB, which is in agreement with the result of TEM photographs. At the same time, we found that the shift of V_FB increased with the increase of the applied constant dc voltage or the thickness of the nc-Si layer.     

Structural evolution of SiNx films deposited by ECR and its light emission

Structural and optical properties of a-SiN_x films deposited by electron cyclotron resonance chemical vapor deposition (ECRCVD) have been investigated. The Fourier transform infrared (FTIR) spectroscopy shows the structural evolution of the SiN_x films, which are defined as Si-rich SiN_x and N-rich SiN_x films, also confirmed by Raman spectroscopy. The origin of the light emission for SiN_x films may be attributed to two mechanisms, i.e., quantum confinement effect (QCE) and transition of defect energy levels. The correlation between light emission and structures of SiN_x films is discussed.     

FABRICATION AND CHARACTERIZATION OF THE SIZE-CONTROLLED AND PATTERNED nc-Si DOTS

A new method of phase-modulated excimer laser crystallization is adopted to fabricate the patterned nanometer-sized crystalline silicon (nc-Si) dots within the sandwiched structure (a-SiN_x:H/a-Si:H/a-SiN_x:H) films. The results of transmission electron microscopy, electron diffraction and Raman scattering show the ultra-thin and single-layer nc-Si films were patterned in the lateral direction and the size of crystallites is controlled by the thickness of as-deposited a-Si film in the longitudinal direction. The effects of the laser energy density on the structures of the samples and the crystallization mechanism are discussed.     

激光干涉结晶技术制备二维有序分布纳米硅阵列

利用结合移相光栅掩模 (PSGM) 的激光结晶技术在超薄a-SiN_x/a-Si:H/ a-SiN _x三明治结构样品中制备出二维有序分布的纳米硅阵列.原始样品是用等离子体 增强化学气相淀积法生长.a-Si:H层厚为10nm，a-SiN_x 为50nm，衬底材料为SiO ₂/Si或 熔凝石英.原子力显微镜、剖面透射电子显微镜、高分辨透射电子显微镜对样品表面形貌和 微结构的观测结果表明，采用该方法可以在原始淀积的a-Si:H层中得到位置可控的晶化区域 ：每个晶化区域直径约250nm，具有同PSGM一致的2μm周期；晶化区域内形成的纳米硅 颗粒尺寸接近原始淀积的a-Si:H层厚，且晶粒的择优取向为<111>. 关键词： 纳米硅 激光结晶 定域晶化 移相光栅     

Thermal annealing of a-Si:H/a-SiNx:H multilayers

The crystallinity of Si/SiN_x multilayers annealed by a rapid thermal process and furnace annealing is investigated by a Raman-scattering technique and transmission electron microscopy. It is found that the crystallization temperature varies from 900 °C to 1000 °C when the thickness of a-Si:H decreases from 4.0 nm to 2.0 nm. Raman measurements imply that the high crystallization temperature for the a-Si:H sublayers originates from the confinement modulated by the interfaces between a-Si:H and a-SiN_x:H. In addition to the annealing temperature, the thermal process also plays an important role in crystallization of a-Si sublayers. The a-Si:H sublayers thinner than 4.0 nm can not be crystallized by furnace annealing for 30 min, even when the annealing temperature is as high as 1000 °C. In contrast, rapid thermal annealing is advantageous for nucleation and crystallization. The origin of process-dependent crystallization in constrained a-Si:H is briefly discussed. Received: 11 April 2001 / Accepted: 20 June 2001 / Published online: 30 August 2001     

Tunneling induced electron transfer in SiNx/AlGaN/GaN based metal-insulator-semiconductor structures

Tunneling induced electron transfer in SiN_x/Al_0.22Ga_0.78N/GaN based metal-insulator-semiconductor (MIS) structures has been investigated by means of capacitance-voltage (C-V) measurements at various temperatures. Large clock-wise hysteresis window in C-V profiles indicates the injection of electrons from the two-dimensional electron gas (2DEG) channel to the SiN_x layer. Depletion of the 2DEG at positive bias in the negative sweeping direction indicates that the charges injected have a long decay time, which was also observed in the recovery process of the capacitance after injection. The tunneling induced electron transfer effect in SiN_x/Al_0.22Ga_0.78N/GaN based MIS structure opens up a way to design Al_xGa_1−xN/GaN based variable capacitors and memory devices.