Exploring the effect of width on performance enhancement in NMOSFETs with a silicon-carbon alloy stressor and a tensile stress silicon nitride liner

The stress distribution in the Si channel regions of a SiC source/drain and stressed silicon nitride liner NMOSFETs with various widths were studied using 3D simulations. The mobility enhancement was found to be dominated by the tensile stress along the transport direction. Stress along the width direction was found to have the least effect on the drain current. The compressive stress along the vertical direction perpendicular to the gate oxide (S_zz) contributes significantly to the mobility enhancement and cannot be neglected in NMOSFETs with a width between 0.05 and 1 μm. The impact of width on performance improvements such as the drive current gain was also analyzed.     

6H-SiC Schottky barrier source／drain NMOSFET with field-induced source／drain extension

A novel SiC Schottky barrier source/drain NMOSFET (SiC SBSD-NMOSFET) with field-induced source/drain (FISD) extension is proposed and demonstrated by numerical simulation for the first time. In the new device the FISD extension is induced by a metal field-plate lying on top of the passivation oxide, and the width of Schottky barrier is controlled by the metal field-plate. The new structure not only eliminates the effect of the sidewalls but also significantly improves the on-state current. Moreover, the performance of the present device exhibits very weak dependence on the widths of sidewalls.     

6H-SiC肖特基源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET——6H-SiC肖特基源漏MOSFET.这种器件结构制备工艺简单，避 免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高、晶格损伤大，注入激活 率低等问题.分析了该器件的电流输运机理，并通过MEDICI模拟，给出了SiC肖特基源漏MOSF ET伏安特性以及其和金属功函数、栅氧化层厚度和栅长关系. 关键词： 碳化硅 肖特基接触 MOSFET 势垒高度     

SiC表面圆环槽边缘效应实验研究

基于固体边缘效应,对碳化硅(SiC)表面激光加工圆环形沟槽的润湿特性进行实验研究,通过分析去离子水在圆环槽上的润湿性能及其在边缘处的铺展行为,获得了环槽深度与环槽宽度对液滴在边缘处最大表观接触角的影响规律.结果表明,SiC圆环槽阻碍液滴铺展,光滑基体表面上接触角为70°,激光加工圆环槽深度为290μm,宽度为1 mm时...     

Non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor with high breakdown voltage

A non-recessed-gate quasi-E-mode double heterojunction AlGaN/GaN high electron mobility transistor(quasi-EDHEMT) with a thin barrier, high breakdown voltage and good performance of drain induced barrier lowering(DIBL)was presented. Due to the metal organic chemical vapor deposition(MOCVD) grown 9-nm undoped AlGaN barrier, the effect that the gate metal depleted the two-dimensiomal electron gas(2DEG) was greatly impressed. Therefore, the density of carriers in the channel was nearly zero. Hence, the threshold voltage was above 0 V. Quasi-E-DHEMT with 4.1-μm source-to-drain distance, 2.6-μm gate-to-drain distance, and 0.5-μm gate length showed a drain current of 260 mA/mm.The threshold voltage of this device was 0.165 V when the drain voltage was 10 V and the DIBL was 5.26 mV/V. The quasi-E-DHEMT drain leakage current at a drain voltage of 146 V and a gate voltage of-6 V was below 1 mA/mm. This indicated that the hard breakdown voltage was more than 146 V.     

Vertical polarization-induced doping InN/InGaN heterojunction tunnel FET with hetero T-shaped gate

A novel vertical InN/InGaN heterojunction tunnel FET with hetero T-shaped gate as well as polarization-doped source and drain region (InN-Hetero-TG-TFET) is proposed and investigated by Silvaco-Atlas simulations for the first time. Compared with the conventional physical doping TFET devices, the proposed device can realize the P-type source and N-type drain region by means of the polarization effect near the top InN/InGaN and bottom InGaN/InN heterojunctions respectively, which could provide an effective solution of random dopant fluctuation (RDF) and the related problems about the high thermal budget and expensive annealing techniques due to ion-implantation physical doping. Besides, due to the hetero T-shaped gate, the improvement of the on-state performance can be achieved in the proposed device. The simulations of the device proposed here in this work show I_ON of 4.45×10^-5 A/μm, I_ON/I_OFF ratio of 10¹³, and SS_avg of 7.5 mV/dec in InN-Hetero-TG-TFET, which are better than the counterparts of the device with a homo T-shaped gate (InN-Homo-TG-TFET) and our reported lateral polarization-induced InN-based TFET (PI-InN-TFET). These results can provide useful reference for further developing the TFETs without physical doping process in low power electronics applications.     

改进型异质栅对深亚微米栅长碳化硅MESFET特性影响

基于器件物理分析方法,结合高场迁移率、肖特基栅势垒降低、势垒隧穿等物理模型, 分析了改进型异质栅结构对深亚微米栅长碳化硅肖特基栅场效应晶体管沟道电势、 夹断电压以及栅下电场分布的影响.通过与传统栅结构器件特性的对比表明, 异质栅结构在碳化硅肖特基栅场效应晶体管的沟道电势中引入了多阶梯分布,加强了近源端电场; 另一方面,相比于双栅器件,改进型异质栅器件沟道最大电势的位置远离源端, 因此载流子在沟道中加速更快,在一定程度上屏蔽了漏压引起的电势变化,更好抑制了短沟道效应. 此外,研究了不同结构参数的异质栅对短沟道器件特性的影响,获得了优化的设计方案, 减小了器件的亚阈值倾斜因子.为发挥碳化硅器件在大功率应用中的优势,设计了非对称异质栅结构, 改善了栅电极边缘的电场分布,提高了小栅长器件的耐压.     

6H-SiC pn结紫外光探测器的模拟与分析

运用器件模拟软件模拟了pn结6H-SiC紫外光探测器的光响应灵敏度特性.讨论了不同掺杂浓度、不同器件结深对响应灵敏度的影响.对于p+n结器件，当受光面为p+层，且厚度约为0.2μm、浓度约为9×10.18cm-3、n层浓度约为1×1 0.16cm-3时，器件有较大的响应灵敏度，R=167.2mA/W；当受光面为n+ 层 ，且厚度约为0.2μm、浓度约为9×10.18cm-3、p层浓度约为1×10.16cm-3时，器件有较大的响应灵敏度，R=183.5mA/W.通过比较可知，模型能较好地反应实际情况，与实验数据符合较好. 关键词： 6H-SiC 紫外光探测 吸收系数 光响应灵敏度     

The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors

At nanometer regime, fabricating the structures with non-overlapped channel and abrupt doping profile is very complicated and sometimes impossible. So, the resultant device experiences some non-ideal effects which have to be predicted and well addressed by simulation before fabrication. In this paper the effects of overlap between gate and source/drain regions on the performance of carbon nanotube field effect transistors have been investigated. The overlapped structure has been simulated with various doping profiles at drain/source and gate region junction tip. The device performance has been investigated in terms of ON current, Off current, ON/Off current ratio, subthreshold swing, delay, and power delay product (PDP). Simulations show that depending on the variations in the effective channel length, the overlap deteriorates some device characteristics and enhances the others. Where the effective channel length decreases (increases), the overlap deteriorates (enhances) the current ratio and subthreshold swing but enhances (deteriorates) the delay and PDP compared to non-overlapped structure. Furthermore, the overlapped structure with graded profile results in lower current ratio and higher subthreshold swing compared to overlapped structure with abrupt profile. At a fixed current ratio, the delay and PDP of overlapped structure with graded profile are more than overlapped structure with abrupt profile but at a fixed channel length, both profiles have approximately equal delay and PDP.     

栅漏间表面外延层对4H-SiC功率MESFET击穿 特性的改善机理与结构优化

本文提出了一种带栅漏间表面p型外延层的新型MESFET结构并整合了能精确描述4H-SiC MESFET工作机理的数值模型,模型综合考虑了高场载流子饱和、雪崩碰撞离化以及电场调制等效应. 利用所建模型分析了表面外延层对器件沟道表面电场分布的改善作用,并采用突变结近似法对p型外延层参数与器件输出电流(I_ds)和击穿电压(V_B)的关系进行了研究.结果表明,通过在常规MESFET漏端处引入新的电场峰来降低栅极边缘的强电场峰并在栅漏之间的沟道表面引入p-n结内建电场进一步降低电场峰值,改善了表面电场沿电流方向的分布.通过与常规结构以及场板结构SiC MESFET的特性对比表明,本文提出的结构可以明显改善SiC MESFET的功率特性.此外,针对文中给定的器件结构,获得了优化的设计方案,选择p型外延层厚度为0.12 μupm,掺杂浓度为5× 10¹⁵ cm^-3,可使器件的V_B提高33%而保持I_ds基本不变.     

SiCGe/SiC 异质结及其光电特性的MEDICI 模拟

在对SiC1-xGex三元合金主要特性的研究基础上，利用器件仿真器MEDICI模拟和分析SiCGe/SiC异质结光电二极管的光电特性。计算表明， SiC1-xGex 在Ge组分为0.3时与3C-SiC晶格失配较小，此时的SiCGe/SiC异质结对可见光和近红外光有较好的光谱响应。当P型SiC1-xGex层杂质浓度为1×1015cm-3、厚度1.6μm、x=0.3时，SiC1-xGex /SiC异质结光电二极管对0.52μm可见光有250mA/W左右的响应度，对0.7μm近红外光也有102mA/W左右的响应度。     

Study on a novel vertical enhancement-mode Ga2O3 MOSFET with FINFET structure

A novel enhanced mode(E-mode)Ga₂O₃ metal-oxide-semiconductor field-effect transistor(MOSFET)with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated.It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics.The metal material of the gate,the oxide material,the oxide thickness,and the epitaxial layer concentration strongly affect the threshold voltage and the output currents.Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant.When the output current density of the device increases,the source concentration,the thickness of the epitaxial layer,and the total width of the device need to be expanded.The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage.It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga₂O₃ MOSFET requires the epitaxial layer concentration,the channel height of the device,the thickness of the source region,and the oxide thickness of the device should be less than 5×10¹⁶ cm^-3,less than 1.5μm,between 0.1μm-0.3μm and less than 0.08μm,respectively.     

SiC1-xGex/SiC 异质结光电二极管特性的研究

使用二维器件模拟软件Medici, 对SiC_1-xGe_x/SiC异质结的光电特性进行了模拟.设计了N型重掺杂SiC层的厚度为1 μm, P型轻掺杂SiC_1-xGe_x层厚为0.4 μm, 二者之间形成突变异质结.在反向偏压3 V、光强度为 0.23 W/cm²的条件下, p-n+ SiC_0.8Ge_0.2/SiC和p-n+ SiC_0.7Ge_0.3/SiC敏感波长λ分别可以达到0.64 μm和0.7 μm, 光电流分别为7.765×10^－7 A/μm和7.438×10^－7 A/μm; 为了进一步提高SiC_1-xGe_x/SiC 异质结的光电流, 我们把p-n+两层结构改进为p-i-n三层结构.在同样的偏压、光照条件下, p-i-n SiC_0.8Ge_0.2/SiC和p-i-n SiC_0.7Ge_0.3/SiC的光电流分别达到1.6734×10－6 A/μm和1.844×10－6 A/μm.     

Schottky barrier MOSFET structure with silicide source/drain on buried metal

In this paper, we propose a novel Schottky barrier MOSFET structure, in which the silicide source/drain is designed on the buried metal (SSDOM). The source/drain region consists of two layers of silicide materials. Two Schottky barriers are formed between the silicide layers and the silicon channel. In the device design, the top barrier is lower and the bottom is higher. The lower top contact barrier is to provide higher {on-state} current, and the higher bottom contact barrier to reduce the off-state current. To achieve this, ErSi is proposed for the top silicide and CoSi₂ for the bottom in the n-channel case. The 50~nm n-channel SSDOM is thus simulated to analyse the performance of the SSDOM device. In the simulations, the top contact barrier is 0.2e~V (for ErSi) and the bottom barrier is 0.6eV (for CoSi₂. Compared with the corresponding conventional Schottky barrier MOSFET structures (CSB), the high on-state current of the SSDOM is maintained, and the off-state current is efficiently reduced. Thus, the high drive ability (1.2mA/μm at V_ds=1V, V_gs=2V) and the high I_on/I_min ratio (10⁶) are both achieved by applying the SSDOM structure.     

基于有限元方法的有机场效应晶体管特性模拟与实验验证

采用有限元方法,借助多物理场软件COMSOL模拟了底栅顶接触结构有机场效应晶体管电位和载流子浓度随源漏电压Vds的变化。模拟结果表明,当固定栅压V_g=-10 V时,改变V_(ds)从0~-10 V,对于电位分布,从栅极到源漏电极竖直方向有渐进的变化,而从源极到漏极的水平方向呈现由大到小明显的梯度变化。对于载流子浓度,观察到沟道处从源极向漏极逐渐减少,在靠近漏极的区域减少得尤为明显,而当源漏电压等于栅极电压时,产生夹断现象。进一步将模拟结果与实际制备的器件性能进行了对比,模拟结果与实验数据所显示的分布趋势大体相同,印证了模拟的合理性。由此表明,采用模拟方法分析有机场效应晶体管的器件特性,对于实际制备器件具有重要的指导意义。     

SiC肖特基源漏MOSFET的阈值电压

SiC肖特基源漏MOSFET的阈值电压不同于传统的MOSFET的阈值电压.在深入分析工作机理的基础上,利用二维模拟软件ISE提取并分析了器件的阈值电压.对SiC肖特基源漏MOSFET的阈值电压给出物理描述,得出当源极载流子主要以场发射方式进入沟道,同时沟道进入强反型状态,此时的栅电压是该器件的阈值电压. 关键词： 碳化硅 肖特基接触 阈值电压     

基于梯度掺杂策略的碳纳米管场效应管性能优化

双极性传输特性是制约碳纳米管场效应管(carbon nanotube field effect transistors,CNFETs)性能提高的一个重要因素.为降低器件的双极性传输特性并获得较大的开关电流比,提出了一种漏端梯度掺杂策略,该策略不仅适合于类MOS碳纳米管场效应管(C-CNFETs),同时也适合于隧穿碳纳米管场效应管(T-CNFETs).基于非平衡格林函数的数值研究结果表明,该策略不仅能有效降低器件的双极传输特性,而且能将器件开关电流比提高数个数量级.进一步研究发现,该掺杂策略在这两类碳纳米管 关键词： 梯度掺杂 带间隧穿 双极性传输 碳纳米管场效应管     

Novel attributes of AlGaN/AlN/GaN/SiC HEMTs with the multiple indented channel

In this paper, a high performance AlGaN/AlN/GaN/SiC High Electron Mobility Transistor (HEMT) with the multiple indented channel (MIC-HEMT) is proposed. The main focus of the proposed structure is based on reduction of the space around the gate, stop of the spread of the depletion region around the source–drain, and decrement of the thickness of the channel between the gate and drain. Therefore, the breakdown voltage increases, meanwhile the elimination of the gate depletion layer extension to source/drain decreases the gate–source and gate–drain capacitances. The optimized results reveal that the breakdown voltage and the drain saturation current increase about 178% and 46% compared with a conventional HEMT (C-HEMT), respectively. Therefore, the maximum output power density is improved by factor 4.1 in comparison with conventional one. Also, the cut-off frequency of 25.2 GHz and the maximum oscillation frequency of 92.1 GHz for the MIC-HEMT are obtained compared to 13 GHz and 43 GHz for that of the C-HEMT and the minimum figure noise decreased consequently of reducing the gate–drain and gate–source capacitances by about 42% and 40%, respectively. The proposed MIC-HEMT shows a maximum stable gain (MSG) exceeding 24.1 dB at 3.1 GHz which the greatest gain is yet reported for HEMTs, showing the potential of this device for high power RF applications.     

纳米体硅鳍形场效应晶体管单粒子瞬态中的源漏导通现象

体硅鳍形场效应晶体管(FinFET)是晶体管尺寸缩小到30 nm以下应用最多的结构,其单粒子瞬态产生机理值得关注.利用脉冲激光单粒子效应模拟平台开展了栅长为30, 40, 60, 100 nm Fin FET器件的单粒子瞬态实验,研究FinFET器件单粒子瞬态电流脉冲波形随栅长变化情况;利用计算机辅助设计(technology computer-aided design, TCAD)软件仿真比较电流脉冲产生过程中器件内部电子浓度和电势变化,研究漏电流脉冲波形产生的物理机理.研究表明,不同栅长Fin FET器件瞬态电流脉冲尾部都存在明显的平台区,且平台区电流值随着栅长变短而增大;入射激光在器件沟道区下方体区产生高浓度电子将源漏导通产生导通电流,而源漏导通升高了体区电势,抑制体区高浓度电子扩散,使得导通状态维持时间长,形成平台区电流;尾部平台区由于持续时间长,收集电荷量大,会严重影响器件工作状态和性能.研究结论为纳米Fin FET器件抗辐射加固提供理论支撑.     

1.3μm GaInNAs量子阱RCE光探测器

采用配有dc-N plasma N源的分子束外延(MBE)技术在GaAs衬底上生长制作了工作波长为1,3μm的GaInNAs量子阱RCE探测器.采用传输矩阵法对器件结构进行优化.吸收区由三个GaInNAs量子阱构成,并用湿法刻蚀和聚酰亚胺对器件进行隔离.在零偏压下,器件最大的量子效率为12%,半峰值全宽(FWHM)为5.8nm,3dB带宽为30MHz,暗电流为2×10^-11A.通过对MBE生长条件和器件结构的优化,将进一步提高该器件的性能.