O2流量对磁控溅射N掺杂TiO2薄膜成分及晶体结构的影响

利用直流脉冲磁控溅射方法在室温下通过改变O₂流量制备具有不同晶体结构的N掺杂TiO₂薄膜,利用台阶仪、X射线光电子能谱仪、X射线衍射仪、紫外-可见分光光度计等设备对薄膜沉积速率、化学成分、晶体结构、禁带宽度等进行分析.结果表明:所制备的薄膜元素配比约为TiO_1.68±0.06N_0.11±0.01,N为替位掺杂,所有样品退火前后均未形成Ti—N相结构,N掺杂TiO₂薄膜的沉积速率、晶体结构等主要依赖于O₂流量.在O₂流量为2 sccm时,N掺杂TiO₂薄膜沉积速率相对较高,薄膜为非晶态结构,但薄膜内含有锐钛矿(anatase)和金红石(rutile)相晶核,退火后薄膜呈anatase和rutile相混合结构,禁带宽度仅为2.86 eV.随着O₂流量的增加,薄膜沉积速率单调下降,退火后样品禁带宽度逐渐增加.当O₂流量为12 sccm时,薄膜为anatase相择优生长,退火后呈anatase相结构,禁带宽度为3.2 eV.综合本实验的分析结果,要在室温条件下制备晶态N掺杂TiO₂薄膜,需在高O₂流量(＞10 sccn)条件下制备. 关键词： 2薄膜')" href="#">N掺杂TiO₂薄膜 磁控溅射 化学配比 晶体结构     

CHx掺杂SiCOH 低介电常数薄膜的物性热稳定性分析

研究了真空热处理对掺CH₄的SiCOH低介电常数薄膜的电流-电压(I-V)特性、电容-电压(C-V)特性、疏水性能以及微结构的影响. 结果表明：在热处理过程中,热稳定性较差的碳氢基团发生了热解吸,使薄膜的漏电流减小、绝缘性能改善,并使薄膜的导电行为更趋于空间电荷限流过程. 碳氢基团的热解吸使SiCOH/Si界面的界面态发生改变,导致SiCOH薄膜MIS结构的平带电压V_FB发生漂移. 封端的碳氢 关键词： SiCOH薄膜 热处理 结构与性能     

基于Si掺杂Sb2Te3薄膜的相变存储器研究

采用磁控三靶(Si，Sb及Te)共溅射法制备了Si掺杂Sb₂Te₃薄膜，作为对比，制备了Ge₂Sb₂Te₅和Sb₂Te₃薄膜，并且采用微加工工艺制备了单元尺寸为10μm×10μm的存储器件原型来研究器件性能.研究表明，Si掺杂提高了Sb₂Te₃薄膜的晶化温度以及薄膜的晶态和非晶态电阻率，使得其非晶态与晶态电阻率之比达到10⁶，提高了器件的电阻开/关比；同Ge₂Sb₂Te₅薄膜相比，16at% Si掺杂Sb₂Te₃薄膜具有较低的熔点和更高的晶态电阻率，这有利于降低器件的RESET电流.研究还表明，采用16at% Si掺杂Sb₂Te₃薄膜作为存储介质的存储器器件原型具有记忆开关特性，可以在脉高3V、脉宽500ns的电脉冲下实现SET操作，在脉高4V、脉宽20ns的电脉冲下实现RESET操作，并能实现反复写/擦，而采用Ge₂Sb₂Te₅薄膜的相同结构的器件不能实现RESET操作. 关键词： 相变存储器 硫系化合物 2Te₃薄膜')" href="#">Si掺杂Sb₂Te₃薄膜 SET/RESET转变     

锰掺杂对Ba(Zr,Ti)O3陶瓷压电与介电性能的影响

采用氧化物固相反应法制备了锰掺杂改性的Ba(Zr_0.06Ti_0.94)O₃陶瓷.研究了锰的掺杂量对Ba(Zr_0.06Ti_0.94)Mn_xO₃ (BZTM)陶瓷的结构、介电和压电性能的影响.实验发现,当锰含量x<0.5 mol%时进入晶格,使材料压电性能提高,损耗减小,表现出受主掺杂的特性;当锰含量x>0.5 mo 关键词： Ba(Zr 3 陶瓷')" href="#">Ti)O₃ 陶瓷 锰掺杂 介电性能 压电性能     

退火对Mn和N共掺杂的Zn0.88Mn0.12O:N薄膜特性的影响

以NH₃为掺N源,采用电子束反应蒸发技术生长了Mn和N共掺杂的Zn_1-xMn_xO:N薄膜,生长温度为300℃,然后在O₂气氛中400℃退火0.5 h.X射线衍射测量表明,Zn_0.88Mn_0.12O(Mn掺杂)薄膜或Zn_0.88Mn_0.12O:N(Mn和N共掺杂)薄膜仍具有单一晶相纤锌矿结构,未检测到杂质相 关键词： ZnO薄膜 Mn和N共掺杂 电学特性 磁特性     

蓝宝石衬底上Gd2O3掺杂CeO2氧离子导体电解质薄膜的生长及电学性能

采用反应磁控溅射方法,在(0001)蓝宝石单晶衬底上,制备了纳米多晶Gd₂O₃掺杂CeO₂(GDC)氧离子导体电解质薄膜,采用X射线衍射仪(XRD)、原子力显微镜(AFM)对薄膜物相、结构、粗糙度、表面形貌等生长特性进行了表征,利用交流阻抗谱仪测试了GDC薄膜不同温度下的电学性能;实验结果表明,GDC薄膜为面心立方结构,在所研究的衬底温度范围内,均呈强(111)织构生长;薄膜表面形貌随衬底温度发生阶段性变化：衬底温度由室温升高到300℃时, 关键词： 2O₃掺杂CeO₂电解质薄膜')" href="#">Gd₂O₃掺杂CeO₂电解质薄膜 反应磁控溅射 生长特性 电学性能     

掺CH4的SiCOH低介电常数薄膜结构与介电性能研究

以十甲基环五硅氧烷和甲烷作为反应气体，采用电子回旋共振等离子体化学气相沉积(ECR-C VD)方法制备了k = 2.45，485℃下的热稳定性优良的SiCOH低介电常数薄膜.通过薄膜结构的 FTIR谱分析，比较了十甲基环五硅氧烷(D5)液态源和不同甲烷流量下制备的薄膜的键结构差 异，发现在沉积过程中甲烷含量的增大，一方面有利于D5源环结构的保留，另一方面有利于 薄膜中形成高密度的CH_n基团.高密度碳氢大分子基团的存在降低了薄膜密度， 结合薄膜中形成的本构孔隙、低极化率Si—C键以及—OH键减少的共同作用，导致薄膜介电 常数的降低. 关键词： 低介电常数 SiCOH薄膜 碳氢掺杂     

Mg,Al掺杂对LiCoO2体系电子结构影响的第一原理研究

为了研究Mg, Al掺杂对锂二次电池正极材料LiCoO₂体系的电子结构的影响，进而揭示Mg掺杂的LiCoO₂具有高电导率的机理，对Li(Co, Al)O₂和Li(Co, Mg)O₂进行了基于密度泛函理论的第一原理研究. 通过对能带及态密度的分析，发现在Mg掺杂后价带出现电子态空穴，提高了电导，并且通过歧化效应（disproportionation）改变了Co-3d电子在各能级的分布，而Al掺杂则没有这些作用. O关键词： 2')" href="#">LiCoO₂ 电子结构 第一原理 电导     

O2掺杂对SiCOH低k薄膜结构与电学性能的影响

以+甲基环五硅氧烷(D5)和氧气(O2)作为反应气体,采用电子回旋共振等离子体化学气相沉积(ECR-CvD)方法制备了κ=2.62的SiCOH薄膜.研究了O2掺杂对薄膜结构与电学性能的影响.结果表明,采用O2掺杂可以在保持较低介电常数的前提下极大地降低薄膜的漏电流,提高薄膜的绝缘性能,这与薄膜中Si-O立体鼠笼、Si-OH结构含量的提高有关.     

非化学计量和掺杂对(Na1/2Bi1/2)0.92Ba0.08TiO3陶瓷电性能的影响

研究了非化学计量和掺杂对无铅压电陶瓷(Na_1/2Bi_1/2)_0.92Ba_0.08TiO₃的压电性能及去极化温度的影响.研究发现A位非化学计量可以提高陶瓷的压电性能;B位掺杂对材料电学性能的影响规律类似于Pb(Ti,Zr)O₃系压电陶瓷的相关规律;由于非化学计量和掺杂会影响到A位离子对B位离子与氧离子形成的BO₆八面体的耦合作用,影响到畴的稳定性,从而影响 关键词： 无铅压电陶瓷 非化学计量 掺杂 电性能     

improvement of electrical properties of Cu/SiCOH low-k film integrated system by O2 plasma treatment

This paper investigates the effect of O2 plasma treatment on the electric property of Cu/SiCOH low dielectric constant （low-k） film integrated structure. The results show that the leakage current of Cu/SiCOH low-k integrated structure can be reduced obviously at the expense of a slight increase in dielectric constant k of SiCOH films. Bythe Fourier transform infrared （FTIR） analysis on the bonding configurations of SiCOH films treated by O2 plasmar it is found that the decrease of leakage current is related to the increase of Si-O cages originating from the linkage of Si dangling bonds through O, which makes the open pores sealed and reduces the diffusion of Cu to pores.     

Si基Bi3.25La0.75Ti3O12铁电薄膜的制备与特性研究

采用Sol-Gel工艺低温制备了Si基Bi_3.25La_0.75Ti₃O₁₂铁电薄膜.研究了退火温度对薄膜微观结构、介电特性与铁电性能的影响.500℃退火处理的Bi_3.25La_0.75Ti₃O₁₂薄膜未能充分晶化，晶粒细小且有非晶团聚，介电与铁电性能均较差.高于550℃退火处理的Bi_3.25La_{0.75 关键词： 铁电薄膜 3.25}La_0.75Ti₃O₁₂')" href="#">Bi_3.25La_0.75Ti₃O₁₂ Sol-Gel工艺     

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al₂O₃ as the gate dielectric, deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8⁰N-/N+ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties (1×10¹⁴ cm^-2) and low gate-leakage current (I_G = 1 × 10^-3 A/cm^-2@E_ox = 8 MV/cm). Analysis of the current conduction mechanism on the deposited Al₂O₃ gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.     

Annealing effects on the structure and electrical characteristics of amorphous Er2O3 films

Amorphous Er 2 O 3 films are deposited on Si (001) substrates by using reactive evaporation.This paper reports the evolution of the structure,morphology and electrical characteristics with annealing temperatures in an oxygen ambience.X-ray diffraction and high resolution transimission electron microscopy measurement show that the films remain amorphous even after annealing at 700 C.The capacitance in the accumulation region of Er 2 O 3 films annealed at 450 C is higher than that of as-deposited films and films annealed at other temperatures.An Er 2 O 3 /ErO x /SiO x /Si structure model is proposed to explain the results.The annealed films also exhibit a low leakage current density (around 1.38 × 10 4 A/cm 2 at a bias of 1 V) due to the evolution of morphology and composition of the films after they are annealed.     

Growth and characterization of crystalline gadolinium oxide on silicon carbide for high- application

We have investigated the growth and electrical properties of crystalline Gd₂O₃ grown on 6H-SiC(0001) substrates by molecular beam epitaxy. Initially, Gd₂O₃ islands with hexagonal structure were formed. Further growth resulted in the formation of flat layers in a mixture of [111]-oriented cubic bixbyite and monoclinic structure. The fabricated capacitors with 14 nm Gd₂O₃ exhibited suitable dielectric properties at room temperature; such as a dielectric constant of ε=22, a leakage current of 10⁻⁸ A/cm²@1 V and breakdown fields >4.3 MV/cm.     

Characterization of Y2O3 gate dielectric on n-GaAs substrates

Physical and electrical properties of sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate are investigated. The as-deposited films and interfacial layer formation have been analyzed by using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). It is found that directly deposited Y₂O₃ on n-GaAs exhibits excellent electrical properties with low frequency dispersion (<5%), hysteresis voltage (0.24 V), and interface trap density (3 × 10¹² eV⁻¹ cm⁻²). The results show that the deposition of Y₂O₃ on n-GaAs can be an effective way to improve the interface quality by the suppression on native oxides formation, especially arsenic oxide which causes Fermi level pinning at high-k/GaAs interface. The Al/Y₂O₃/n-GaAs stack with an equivalent oxide thickness (EOT) of 2.1 nm shows a leakage current density of 3.6 × 10⁻⁶ A cm⁻² at a V_FB of 1 V. While the low-field leakage current conduction mechanism has been found to be dominated by the Schottky emission, Poole-Frenkel emission takes over at high electric fields. The energy band alignment of Y₂O₃ films on n-GaAs substrate is extracted from detailed XPS measurements. The valence and conduction band offsets at Y₂O₃/n-GaAs interfaces are found to be 2.14 and 2.21 eV, respectively.     

Stabilization of a very high-k crystalline ZrO2 phase by post deposition annealing of atomic layer deposited ZrO2/La2O3 dielectrics on germanium

The impact of the ZrO₂/La₂O₃ film thickness ratio and the post deposition annealing in the temperature range between 400 °C and 600 °C on the electrical properties of ultrathin ZrO₂/La₂O₃ high-k dielectrics grown by atomic layer deposition on (1 0 0) germanium is investigated. As-deposited stacks have a relative dielectric constant of 24 which is increased to a value of 35 after annealing at 500 °C due to the stabilization of tetragonal/cubic ZrO₂ phases. This effect depends on the absolute thickness of ZrO₂ within the dielectric stack and is limited due to possible interfacial reactions at the oxide/Ge interface. We show that adequate processing leads to very high-k dielectrics with EOT values below 1 nm, leakage current densities in the range of 0.01 A/cm², and interface trap densities in the range of 2-5 × 10¹² eV⁻¹ cm⁻².     

Structure and electrical properties of HfO<Subscript>2</Subscript> high-<Emphasis Type="Italic">k</Emphasis> films prepared by pulsed laser deposition on Si (100)

High-k gate dielectric hafnium dioxide films were grown on Si (100) substrate by pulsed laser deposition at room temperature. The as-deposited films were amorphous and that were monoclinic and orthorhombic after annealed at 500°C in air and N₂ atmosphere, respectively. After annealed, the accumulation capacitance values increase rapidly and the flat-band voltage shifts from −1.34 V to 0.449 V due to the generation of negative charges via post-annealing. The dielectric constant is in the range of 8–40 depending on the microstructure. The I–V curve indicates that the films possess of a promising low leakage current density of 4.2×10⁻⁸ A/cm² at the applied voltage of −1.5 V.     

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)