Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control by Means of Dynamic Biasing

Two new class AB output stages for CMOS op-amps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Using these stages two opamps have been designed using a 0.8 m CMOS technology. Experimental results show a unity gain frequency of 15 MHz with 290 A of quiescent current and a 10 pF load, using a 1.5 V single voltage supply.     

Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultra-low supply voltage operation also in CMOS processes with high threshold voltages. This paper presents the theoretical basis for the design of V_T0n = | V_T0p | = 0.9VV_{T0n} = \left| {V_{T0p} } \right| = 0.9V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than ±18 A with a supply voltage down to 1 V, and relatively small device dimensions. In spite of the relatively large signal processing range, the class AB operation of the cell enabled a very low quiescent current consumption, 1 A in this design, resulting in a very high current efficiency and effective power consumption, as well as good noise performance.     

Winner-Take-All Class AB Input Stage

A novel technique to implement class AB differential amplifier input stages is proposed. It is based on the use of Winner-Take-All circuits for achieving dynamic current boosting, and is well suited for low-voltage operation. Experimental measurements of an OTA using this technique, fabricated in a 0.5-μm CMOS technology, show a slew rate of 92 V/μs for an 80-pF load and 120 μW of static power consumption.     

Very Low Voltage Rail-to-Rail Programmable-Gain CMOS Amplifier

A novel design technique for operating closed-loop amplifier circuits at very low supply voltages is proposed. It is based on the use of quasi-floating gate transistors, avoiding issues encountered in true floating-gate structures such as the initial floating-gate charge, offset drift with temperature, and the gain-bandwidth product degradation. A programmable-gain differential amplifier is designed and implemented following this method. Measurement results of an experimental prototype fabricated in a 0.5-m CMOS technology validate on silicon the proposed technique.     

Low Voltage CMOS Power Amplifier with Rail-to-Rail Input and Output

This paper describes a CMOS power amplifier with rail-to-rail input and output, also suitable for low voltage applications. The amplifier uses Simple Miller Compensation with high bandwidth stage to robustly and power efficiently compensate the amplifier. Circuit also includes a common mode adapter block, based on resistive level shift network, to implement rail-to-rail input and optional adaptive biasing block, which can be used to extend bandwidth of the amplifier for large high frequency inputs in continuous-time applications. Measurement results show that the amplifier is capable of driving heavy resistive and capacitive loads having maximum output current exceeding 100 mA, when driving 1 nF ‖ 10 Ω load from 3.0 V supply. Without adaptive biasing the linear amplifier achieves 5.7 MHz unity gain frequency and 61^∘ phase margin when driving 1 nF ‖ 1 kΩ load, while drawing 2.4 mA from 1.5 V supply.     

Very Low Voltage CMOS Current Multiplier with Floating DC Level Shifters

A compact, wide dynamic range, four-quadrant analog CMOS current multiplier is presented. The use of floating DC level shifters (floating batteries) made by resistors and current sources allows low supply voltages while maintaining at the same time a large input range and low harmonic distortion. Measurement results for an experimental prototype in a 0.8 m CMOS technology demonstrate on silicon the proposed technique.     

一种基于准浮栅技术的新型低压全差分运算放大器

讨论分析了准浮栅晶体管的工作原理、电气特性及其等效电路。基于准浮栅 PMOS 晶体管,设计实现了全差分运算放大器。在 1.3V 的单电源电压下,运算放大器的最大开环增益为 63.7dB,相位裕度为 63°,单位增益带宽为26.1MHz。利用本文设计的准浮栅全差分运放,设计实现了增益可调的放大器。     

Input/Output Rail-to-Rail CMOS Operational Amplifier with Shaped Common-Mode Response

This paper presents an input/output rail-to-rail class-AB CMOS operational amplifier with reduced variations in unity-gain frequency over the entire voltage range. The rail-to-rail amplifier input stage is based on two parallel-connected complementary differential pairs. Variations in the small-signal response are kept to a minimum by realizing an adequate shaping of the CM response of the input stage, while still reducing deviations in the total limiting current of the two input pairs with respect to traditional solutions. This is achieved independently of the g _m -I _D characteristic of the amplifier input devices and of any strict matching condition between the complementary input pairs. Experimental results from a 3-V 0.8-m CMOS test-chip are given.     

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Organic field‐effect transistor (FET) memory is an emerging technology with the potential to realize light‐weight, low‐cost, flexible charge storage media. Here, solution‐processed poly[9,9‐dioctylfluorenyl‐2,7‐diyl]‐co‐(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top‐gate/bottom‐contact device configuration is reported. A reversible shift in the threshold voltage (V_Th) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross‐linked poly(4‐vinylphenol). The F8T2 NFGM showed relatively high field‐effect mobility (µ_FET) (0.02 cm² V^?1 s^?1) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10⁴) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top‐gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.     

Alternative Realizations of CMOS Current Feedback Amplifiers for Low Voltage Applications

Two variants of a new current feedback amplifier (CFA) are presented in this paper. These CFAs are realized in CMOS technology and both are capable of working at low voltages. It is shown that one circuit performs better than the other by virtue of an increased impedance at its Z terminal achieved through the use of additional transistors. Analysis of both variants of the current conveyor and buffer that form the current feedback amplifier gives an insight into the location of primary poles and zeros of the CFAs. Simulation results indicate an overall gain bandwidth product in excess of 59 MHz and 102 MHz for each circuit at a gain of –10 and with a 3.3 V supply. Experimental results from a chip fabricated in a 0.35 m CMOS technology agree closely with the simulation results.     

低电压CMOS模拟集成运算放大器输入级的研究

对于低电压CMOS模拟集成运算放大器输入级所面临的问题,我们提出了三种解决的方法,其中包括输出为Rail—to—Rail的差分输入放大电路,差分输入的互导为恒定值的差分输入电路(假设KN=KP)和差分输入的互导为常数的差分输入电路(KN≠KP)。分别对三种方法进行了详细的分析和讨论,最后,提出了低电压CMOS模拟集成运算放大器输入级还需要解决的问题。     

一种无运放低压低功耗CMOS带隙基准电压源的设计

采用无运放电路结构,通过改进反馈环路和调整电阻的方法,设计了一种低电压低功耗的带隙基准电压源.相比传统有运放结构,电路芯片面积更小和具有更低的电流损耗,并且大部分电流损耗都用于产生输出电压.基于CSMC 0.5 μmCMOS工艺对所研制带隙基准电压源进行流片,测试结果表明,当电源电压大于0.85 V时,能够产生稳定的输...     

A Very Low Voltage Bipolar Op-Amp for Sensor Applications

A new bipolar four-quadrant operational amplifier operating at a power supply voltage of 0.8 V and with a supply current of 800 A is here presented and illustrated. It features low input offset, low bias current, low noise, low crossover distortion and a rail-to-rail output swing. Control circuits ensuring minimum and maximum current limits for the output transistors have been incorporated. The biasing circuitry follows a PTAT scheme. A simple compensation topology allows the reduction of the area. The chip, whose area is about 2 mm², has been fabricated in HF2CMOS 2 /6 GHz technology. Finally, Spice simulations and experimental results, which confirm the expected overall performances of the low voltage op-amp, are reported.     

采用多次离子注入调整亚微米CMOS电路的阈电压

采用多次离子注入来调整亚微米CMOS的NMOS和PMOS管的阈值电压是研究亚微米CMOS电路的关键.浅离子注入调节表面掺杂浓度以达到调整阈值电压的目的.深离子注入调整源漏穿通电压.与LDD、硅化物工艺相合,已研制出0.5μm的CMOS 27级环振电路,门延迟为130ps.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.