A Flexible Programmable Memory BIST for Embedded Single‐Port Memory and Dual‐Port Memory

Programmable memory built‐in self‐test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single‐port memory and dual‐port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.     

低成本BIST映射电路的设计与优化

低成本BIST利用映射电路对自测试线形反馈移位寄存器进行优化,将对故障覆盖率无贡献的测试向量屏蔽掉,有效提高了故障覆盖率,降低了测试功耗。映射电路的设计是低成本BIST设计的关键,为了降低其硬件开销和功耗、提高参数性能,该映射逻辑电路对测试向量的种子进行映射,并通过相容逻辑变量合并、布尔代数化简等方法对映射电路进行优化,有效地降低了测试应用时间、测试功耗和硬件开销。     

面向低功耗BIST 的VLSI 可测性设计技术

随着手持设备的兴起和芯片对晶片测试越来越高的要求，内建自测试的功耗问题引起了越来越多人的关注，本文对目前内建自测试的可测性设计技术进行了分析并对低功耗的VLSI可测性设计技术的可行性和不足分别进行了探讨。在文章的最后简单介绍了笔者最近提出的一种低功耗的BIST结构。     

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs

In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re-using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead.Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.     

A counter-based pseudo-exhaustive pattern generator for BIST applications

Built-in self test (BIST) has been accepted as an efficient alternative to external testing, since it provides for both test generation and response verification operations, on chip. Pseudo-exhaustive BIST generators provide 100% fault coverage for detectable combinational faults with much fewer test vectors than exhaustive testing. An (n,k) adjacent bit pseudo-exhaustive test set (PETS) is a set of n-bit vectors in which all 2^k binary combinations appear to all adjacent k-bit groups of inputs.In this paper a novel, counter-based pseudo-exhaustive BIST generator is presented, termed pseudo-exhaustive counter (PEC). An n-stage PEC can generate (n,k) adjacent bit PETS for any value of k, k<n. This kind of testing is termed Generic pseudo-exhaustive testing. A Generic pseudo-exhaustive generator can be used to pseudo-exhaustively test more than one module. The PEC scheme is then extended to recursively generate all (n,k) adjacent bit pseudo-exhaustive tests sets for k<=n. This kind of testing is termed progressive pseudo-exhaustive testing in the literature; α progressive pseudo-exhaustive generator can pseudo-exhaustively test more than one modules in parallel.Comparisons of PEC with techniques proposed in the literature that can be used for Generic and Progressive pseudo-exhaustive testing reveal that PEC is more effective in terms of both hardware overhead and time required to complete the test.     

ASIC可测试性设计技术

可测性设计技术对于提高军用ＡＳＩＣ的可靠性具有十分重要的意义。结合可测性设计技术的发展,详细介绍了设计高可靠军用ＡＳＩＣ时常用的ＡｄＨｏｃ和结构化设计两种可测性技术的各种方法,优缺点及使用范围。其中,着重论述了扫描技术和内建自测试技术。     

内建自测试中移位器的设计及其应用

本文提出了一种新的方法和综合技术用来去除多扫描链内建测试中由线形反馈移位寄存器引起的测试向量线性关联性，利用本方法可以高效的设计内建自测试中移位器并且保证足够扫描链间的位移和每条扫描通道尽少量的门数开销。     

An Accumulator-Based BIST Approach for Two-Pattern Testing

Two-pattern tests target the detection of most common failure mechanisms in cmos vlsi circuits, which are modeled as stuck-open or delay faults. In this paper the Accumulator-Based Two-pattern generation (ABT) algorithm is presented, that generates an exhaustive n-bit two-pattern test within exactly 2 ⁿ × (2 ⁿ – 1) + 1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implementation) or a Linear Feedback Shift Register (LFSR-based implementation). With the counter-based implementation different modules, having different number of inputs, can be efficiently tested using the same generator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (that typically drive the accumulator inputs into dapatapath cores) can be easily modified to LFSRS with small increase in the hardware overhead. The great advantage of the presented scheme is that it can be implemented by augmening existing datapath components, rather than building a new pattern generation structure.     

基于全状态伪随机序列的BIST设计

全状态伪随机序列发生器（ASPRG）是在FSR的基础上,通过修改其反馈函数而得到,其最大的优点就是利用了移位寄存器的全部状态,序列最大长度为2^n。本文首先推导得到4位和8位ASPRG的反馈网络函数,在此基础上应用ASPRG进行内建自测试（Build In Self Test）设计并优化电路结构,ASPRG既作为测试信号发生器,而它的另一种工作模式则作为特征分析使用。这样不仅简化了BIST设计,同时降低了功耗,具有较高的现实意义。     

大规模集成电路可测性设计及其应用策略

随着集成电路的规模不断增大,集成电路的可测性设计正变得越来越重要.综述了可测性设计方案扫描通路法、内建自测试法和边界扫描法,并分析比较了这几种设计方案各自的特点及应用策略.     

一种减少BIST测试资源的高级寄存器分配算法

在高级综合阶段考虑电路的可测性有许多优点，包括降低硬件开销，减少性能的下降，并达到更高的测试效率等。本文提出了一种基于伪随机可测性方法的寄存器分配算法，来减少内建自测试（BIST）所带来的硬件开销。在基准电路上的实验结果表明：与其它BIST测试综合方法相比较，采用本论文所提的方法进行测试综合对测试资源占用最多可以降低46.8%.     

An effective BIST scheme for SRAM full speed test

This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55?nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3?GHz, and the test precision is about 35?ps at the typical process corner with supply voltage 1.0?V and temperature 25°C.     

Design of Multi‐time Programmable Memory for PMICs

In this paper, a multi‐time programmable (MTP) cell based on a 0.18 μm bipolar‐CMOS‐DMOS backbone process that can be written into by using dual pumping voltages — VPP (boosted voltage) and VNN (negative voltage) — is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p‐wells are used — one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n‐well is used for the 256‐bit MTP cell array. In addition, a three‐stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of and a user memory area of , is newly proposed in this paper.     

面向系统芯片的可测性设计

随着集成电路的规模不断增大,芯片的可测性设计正变越来越重要。回顾了一些常用的可测性设计技术,分别讨论了系统芯片（SOC）设计中的模块可测性设计和芯片可测性设计策略。     

GPS基带芯片中存储器的可测性设计

GPS基带芯片中嵌入的存储器采用存储器内建自测试(Memory Built-in-Self-Test,MBIST)技术进行可测性设计,并利用一种改进型算法对存储器内建自测试电路的控制逻辑进行设计,结果表明整个芯片的测试覆盖率和测试效率均得到显著提高,电路性能达到用户要求,设计一次成功.     

基于内建自测技术的Mesh结构NoC无虚通道容错路由算法

 在Zhang's算法绕行思想的基础上,提出了一种2D-Mesh结构片上网络无虚通道容错路由算法,用于解决多故障节点情况下片上网络的无虚通道容错路由问题.算法利用内建自测试机制获取故障区域的位置信息,通过优化绕行策略来均衡故障区域周围链路的负载并减少部分数据的绕行距离.针对8×8的2D-Mesh网络的仿真表明,与Chen's算法相比,在故障区域大小为2×2,网络时延为70 cycles的情况下,随着故障区域位置的变化所提算法可提高1.2%到4.8%的网络注入率.且随着故障区域面积的扩大,所提算法在减少通信时延,提高网络吞吐量方面的作用更为明显.     

A new on-chip digital BIST for analog-to-digital converters

A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminates the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using Mitel CMOS 1.5 μm technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converters or high resolution pipelined analog-to-digital converters. The presented BIST shows satisfactory results for a nine-bit pipe-lined analog-to-digital converter.     

Dynamic Self‐Repair Architectures for Defective Through‐silicon Vias

Three‐dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through‐silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built‐in self‐test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self‐repair architectures using code‐based and hardware‐mapping based repair.     

A Novel Design Strategy for Fully Physically Linked Double Network Hydrogels with Tough,Fatigue Resistant,and Self‐Healing Properties

Double network (DN) hydrogels with two strong asymmetric networks being chemically linked have demonstrated their excellent mechanical properties as the toughest hydrogels, but chemically linked DN gels often exhibit negligible fatigue resistance and poor self‐healing property due to the irreversible chain breaks in covalent‐linked networks. Here, a new design strategy is proposed and demonstrated to improve both fatigue resistance and self‐healing property of DN gels by introducing a ductile, nonsoft gel with strong hydrophobic interactions as the second network. Based on this design strategy, a new type of fully physically cross‐linked Agar/hydrophobically associated polyacrylamide (HPAAm) DN gels are synthesized by a simple one‐pot method. Agar/HPAAm DN gels exhibit excellent mechanical strength and high toughness, comparable to the reported DN gels. More importantly, because the ductile and tough second network of HPAAm can bear stress and reconstruct network structure, Agar/HPAAm DN gels also demonstrate rapid self‐recovery, remarkable fatigue resistance, and notable self‐healing property without any external stimuli at room temperature. In contrast to the former DN gels in both network structures and underlying association forces, this new design strategy to prepare highly mechanical DN gels provides a new avenue to better understand the fundamental structure‐property relationship of DN hydrogels, thus broadening current hydrogel research and applications.