Partially depleted SOI MOSFETs under uniaxial tensile strain

The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 /spl mu/m. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 /spl mu/m, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.     

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for     

Hysteresis effect in floating-body partially depleted SOI CMOS domino circuits

This paper investigates in detail the basic mechanisms of hysteretic delay and noise margin variations for floating-body partially depleted SOI CMOS domino circuits. We first consider the ‘clock cycling scenario’, which completely eliminates (or isolates) the hysteresis effect of the output inverter, thus allowing one to observe and understand the hysteresis effect of the front-end domino logic stage. Three cases, based on whether the input signals are domino input signals, from other domino circuits, static input signals, from static circuits or latches; or a combination of domino and static input signals, are examined and differentiated. It is shown that hysteretic delay variation is the largest and the noise margin worst for the case with mixed domino and static input signals. Although the delay and noise margin disparities among the three types of input signals are significant at the beginning of the clock cycles, they converge as the circuit approaches steady state. The ‘data cycling scenario’ with the combined hysteresis effect of both the front-end domino logic stage and the output inverter is then discussed. Circuits operating under the ‘data cycling scenario’ are shown to have less body charge loss through the switching cycles than under the ‘clock cycling scenario’.     

Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits

This paper presents a new circuit technique to alleviate the uncontrollable floating-body-induced hysteretic component present in the transfer characteristics of voltage-mode CMOS Schmitt trigger circuits in a partially depleted silicon-on-insulator technology. This technique integrates a successive switching threshold shift mechanism with the systematic body contact scheme, resulting in improved noise immunity and well-defined hysteresis behavior for the Schmitt trigger circuit that is suitable for use as a low-noise receiver, level shifter, waveform-reshaping circuit, and delay element in very large-scale integrated applications.     

On the transient operation of partially depleted SOI NMOSFET's

The transient operation of partially depleted (PD) Silicon-On-Insulator (SOI) NMOSFET's is investigated, based on two-dimensional numerical simulations. The studied devices have a gate length of 0.2 μm and a floating body. They are designed for a supply voltage of 2 V. In the case of gate transient, we show that the body voltage is more influenced by the capacitive coupling with the gate electrode than the impact ionization current. Further, we demonstrate, for the first time, that the anomalous subthreshold slope, that exists in a DC static transfer I-V curve, does not exist in fast transient mode because the minimum time constant for body charging by impact ionization current is on the order of 3 ns in such devices     

Low-voltage arithmetic units based on fully depleted SOI CMOS nanotransistors

Approaches to the development of low-voltage low-power-demand arithmetic units on the basis of silicon-on-insulator nanotransistors are considered. The characteristics of physical models of one- and eight-bit adders based on fully depleted silicon-on-insulator complementary metal-oxide-semiconductor nanotransistors with different topological parameters are numerically analyzed. For some selected elements, the dependences of the delay time and switching power on supply voltage below 1 V are studied for different voltages at the back gate of the transistor.     

EOS/ESD reliability of partially depleted SOI technology

A model for predicting the electrostatic discharge (ESD) protection level of PD-SOI MOSFETs and diodes is presented along with data to support the model. The form of the model is compatible with circuit simulators. An important design rule for layout of multifinger SOI ESD protection MOSFETs has been derived from the model. We present experimental data to support this design rule     

A comparison of floating-body potential in H-gate ultrathin gate oxide partially depleted SOI pMOS and nMOS devices based on 90-nm SOI CMOS process

Based on a 90-nm silicon-on-insulator (SOI) CMOS process, the floating-body potential of H-gate partially depleted SOI pMOS and nMOS devices with physical gate oxide of 14 /spl Aring/ is compared. For pMOS devices, because the conduction-band electron (ECB) tunneling barrier is lower (/spl cong/3.1 eV), the ECB direct-tunneling current from the n/sup +/ poly-gate beside the body terminal will contribute to a large amount of electron charges into the neutral region and dominate the floating-body potential under normal operations. Conversely, owing to the higher valence-band hole tunneling barrier (/spl cong/4.5 eV), the floating-body potential of nMOS devices is dominated by the band-to-band-tunneling mechanism at the drain-body junction, not the direct-tunneling mechanism.     

Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices

This paper reports the dc performance enhancements of partially depleted (PD) silicon-on-insulator (SOI) devices with lower subthreshold swing and higher driving capability, kink-onset voltage, and transconductance simultaneously. Based on the measured results, by using layout technique, for floating-body PD SOI pMOSFETs with ultrathin gate-oxide thickness, H-gate configuration with the partial n/sup +/ poly-gate shows the best floating-body characteristics as compared to that in T-gate and three-terminal configurations. Owing to the direct-tunneling mechanism in the partial n/sup +/ poly-gate, the conduction-band electron tunneling current will make the floating-body potential biased in strong inversion region raised. In addition, due to the larger oxide voltage drop across the partial n/sup +/ poly-gate in subthreshold region, the valence-band hole substrate current will result in lower floating-body potential. These dc performance enhancements advantage in both digital and analog designs.     

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs

The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.     

Effect of starting SOI material quality on low-frequency noise characteristics in partially depleted floating-body SOI MOSFETs

The low-frequency noise properties of partially-depleted (PD) floating-body silicon-on-insulator (SOI) MOSFETs fabricated on two types of commercially available bonded SOI (BSOI) wafers were experimentally investigated. In the pre-kink region, a drain bias dependent Lorentzian-like noise has been observed for UNIBOND wafers, while a pure 1/f noise has been achieved for ELTRAN wafers. Our analysis shows that the charge fluctuation induced by emission process through intermediate-level centers in the drain-depletion region causes the instability in the body voltage, resulting in the pre-kink excess noise for UNIBOND wafers.     

Temperature dependency of 0.1 μm partially depleted SOI CMOSFET

This work investigates the floating body effect (FBE) on the partially depleted SOI devices at various temperatures for high-performance 0.1 μm MOSFET. The thermal effect on the device's characteristics was investigated with respect to the body contacted MOSFET (BC-SOI) and floating body MOSFET without body contacted (FB-SOI). It is found that the threshold voltage (Vth) and the off state drain current (I_OFF) of the BC-SOI devices are more temperature sensitive than those of the FB-SOI devices. For operation at higher temperatures, there is no apparent difference in driving capability between the BC-SOI and FB-SOI MOSFETs     

轴向应变导致柔性电路的裂化研究

本文研究了在柔性塑料衬底上的均匀的无定形si和siN。薄膜的裂化规律。结果表明，在单轴向拉力应变下，虽然衬底仍保持完整，但是半导体薄膜破裂为直的并行的阵列。当应变大于一个临界值后，裂纹的密度成线性增长。用原子力显微镜对裂纹的宽度和深度进行了表征和分析。     

Effects of floating body on double polysilicon partially depleted SOI nonvolatile memory cell

The floating-body effect of nonvolatile memory cells fabricated using partially depleted silicon-on-insulator (SOI) technology has been investigated using two-dimensional numerical device simulation. Compared with similar bulk devices, the floating-body effect of partially depleted SOI MOSFETs introduces instability in the value of the drain current during sensing and extra hot-electron gate current in programming. The effects of the drain-current instability on the error margins in read operation are studied. The floating-body effect is found to be heavily dependent on biasing condition.     

On the temperature dependence of hysteresis effect in floating-bodypartially depleted SOI CMOS circuits

This paper presents a detailed study on the temperature dependence of the hysteresis effect in static CMOS circuits and pass-transistor-based circuits with floating-body partially depleted (PD) silicon-on-insulator (SOI) CMOS devices. Basic physical mechanisms underlying the temperature dependence of hysteretic delay variations are examined. It is shown that, depending on the initial state of the circuit, the initial circuit delays have distinct temperature dependence. For steady-state circuit delays, the temperature dependence is dictated solely by the various charge injection/removing mechanisms into/from the body. The use of the cross-coupled dual-rail configuration in pass-transistor-based circuits is shown to be effective in compensating and reducing the disparity in the temperature dependence of the delays     

High performance and highly reliable novel CMOS devices using accumulation mode multi-gate and fully depleted SOI MOSFETs

In this paper, the electrical characteristics of multi-gate MOSFETs (MUGFETs) using the advanced radical gate oxide and a suppression of Negative bias temperature degradation in accumulation mode FD-SOI MOSFETs are described. Firstly, we experimentally demonstrate that the multi-gate MOSFETs using radical oxide effectively suppress the degradation of S-factor values resulted from its superior oxidation at the sidewall. Secondly, we indicate that the device performance is dramatically improved by introducing MUGFETs device structure originated from its effective channel area. Finally, we reveal the improvement of current drivability and a suppression of Negative bias temperature instability (NBTI) in accumulation mode FD-SOI MOSFETs.     

CMOS on dual SOI thickness for optimal performance

A novel strained SOI process with dual SOI thickness has been demonstrated for the first time. Two different SOI thicknesses (Tsi) are obtained on the same wafer for n- and p-channel devices using one additional photo masking step. Device data shows the S/D junction capacitance is reduced by 12% without any degradation in the driving current. A thicker SOI is used for p-channel devices to increase the SiGe recess depth and volume for the embedded S/D SiGe. The driving current is improved by 15% as a result of the larger compressive stress compared to a smaller SOI thickness. Dual SOI thickness is proved to be a viable strategy for independently optimizing n- and p-channel devices.     

Computer-aided performance assessment of fully depleted SOI CMOSVLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies     

On negative differential resistance in hydrodynamic simulation of partially depleted SOI transistors

We show that the negative differential resistance in the I/sub d/-V/sub ds/ characteristics observed in hydrodynamic transport simulations of partially depleted silicon-on-insulator MOSFETs disappears if the nonlocality of tunneling effects are properly accounted for in the recombination-generation process.