Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit

Reversible logic is emerging as a promising alternative for applications in low-power design and quantum computation in recent years due to its ability to reduce power dissipation, which is an important research area in low power VLSI and ULSI designs. Many important contributions have been made in the literatures towards the reversible implementations of arithmetic and logical structures; however, there have not been many efforts directed towards efficient approaches for designing reversible Arithmetic Logic Unit (ALU). In this study, three efficient approaches are presented and their implementations in the design of reversible ALUs are demonstrated. Three new designs of reversible one-digit arithmetic logic unit for quantum arithmetic has been presented in this article. This paper provides explicit construction of reversible ALU effecting basic arithmetic operations with respect to the minimization of cost metrics. The architectures of the designs have been proposed in which each block is realized using elementary quantum logic gates. Then, reversible implementations of the proposed designs are analyzed and evaluated. The results demonstrate that the proposed designs are cost-effective compared with the existing counterparts. All the scales are in the NANO-metric area.     

A Unique Reversible Gate in Quantum-dot Cellular Automata for Implementation of Four Flip-flops Without Garbage Outputs

In this paper, a unique gate is presented for the design of reversible flip-flops in quantum-dot cellular automata technology. The proposed gate is implemented with multiplexer, three-input Majority gate and XOR gate. The proposed gate has four input lines and four output lines. This gate is designed without garbage outputs. In other words, each output determines the function of each of flip-flops. The proposed structure is evaluated by the QCADesigner. The result of the simulation represents that the operations of the proposed structure is as expected and all functions are correct. Also, the evaluation results show that the proposed structure has significant improvement in area, cell numbers and delay compared to the previous structures. QCAPro tool is used to estimate energy consumption of the proposed structure.     

Modified signed-digit addition by using binary logic operations and its optoelectronic implementation

In this work, a three-step modified signed-digit (MSD) addition by using binary logic operations is proposed. Each input digit is encoded with two binary bits. Through binary logic operations, all of the weight and transfer digits and the final sum digits represented with the same encoding scheme will be generated. The operations can be performed at each digit position in parallel. In our suggested optical arithmetic and logic unit (ALU), a single electron trapping (ET) device is employed to serve as the binary logic device. This technique based on ET logic possesses the advantage of high signal-to-noise ratio (SNR). The optoelectronic system can be constructed in a simple, compact and general-purpose form.     

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

     

A secret image sharing based on neighborhood configurations of 2-D cellular automata

The main goal of this work is to research how neighborhood configurations of two-dimensional cellular automata (2-D CA) can be used to design secret sharing schemes, and then a novel (n, n)-threshold secret image sharing scheme based on 2-D CA is proposed. The basic idea of the scheme is that the original content of a 2-D CA can be reconstructed following a predetermined number of repeated applications of Boolean XOR operation to its neighborhood. The main characteristics of this new scheme are: each shared image has the same size as the original one; the recovered image is exactly the same as the secret image, i.e., there is no loss of resolution or contrast; and the computational complexity is linear. Simulation results and formal analysis demonstrate the correctness and effectiveness of the proposed sharing scheme.     

Trinary arithmetic and logic unit (TALU) using savart plate and spatial light modulator (SLM) suitable for optical computation in multivalued logic

Arithmetic logic unit (ALU) is the most important unit in any computing system. Optical computing is becoming popular day-by-day because of its ultrahigh processing speed and huge data handling capability. Obviously for the fast processing we need the optical TALU compatible with the multivalued logic. In this regard we are communicating the trinary arithmetic and logic unit (TALU) in modified trinary number (MTN) system, which is suitable for the optical computation and other applications in multivalued logic system. Here the savart plate and spatial light modulator (SLM) based optoelectronic circuits have been used to exploit the optical tree architecture (OTA) in optical interconnection network.     

Toward Efficient Design of Flip-flops in Quantum-Dot Cellular Automata with Power Dissipation Analysis

Quantum-dot cellular automata (QCA) is one of the emergent nano-technologies and a potential substitute for transistor based technologies. In this research, an efficient QCA based T, SR and JK flip-flops have been proposed. The proposed gates are implemented with multiplexer, three-input Majority gate and XOR gate. The circuit layouts are designed and verified using QCADesigner version 2.0.3. The simulation result reviles the excellence of the proposed design. The proposed T flip-flop archives 35% improvement in terms cell count. Similarly, the reported RS and JK flip-flop requires 43% and 50% less area respectively in comparison to the previous best single layer design. In addition, QCAPro tool has been used to estimate the power dissipation of all considered designs at different tunneling energy level.     

Optical implementation of the stream cipher based on the irreversible cellular automata algorithm

A hybrid optical scheme for efficient hardware implementation of the one-dimensional, three-neighborhood binary cellular automata rule a(i)(?) =a(i-1)XOR(a(i)OR a(i+1)) -based stream cipher is proposed. The system makes full use of the parallel, space-invariant, cascadable, and modular structure of the algorithm and is simple, robust, and compact. The number of cellular automata arrays can be as large as the number of pixels on the spatial light modulator, which results in an increase in speed (number of bits operated in parallel) and security (key length). The system can be made fully optical with the use of an optically addressable spatial light modulator for the input plane and for the nonlinear threshold element.     

Performance enhancement of UV quantum well light emitting diode through structure optimization

Optical and Quantum Electronics - Arithmetic logic unit (ALU) is the core of any digital processing systems. For creating an all optical ALU one needs basic logic gates such as optical NOT, OR and...     

二维光子晶体全光异或门的设计及研究

分析了二维光子晶体马赫-曾德尔干涉仪的传输特性,将二维光子晶体波导、环形腔和马赫-曾德尔干涉仪有效结合,提出了一种基于二维光子晶体马赫-曾德尔干涉仪的异或门设计。用平面波展开法分析二维光子晶体能带结构,并用时域有限差分法验证光信号在该器件中的电场稳态分布。结果表明,该结构能够实现异或逻辑,且具有高逻辑对比度7.88 dB,快速响应周期0.388 ps和高传输速率7.87 Tbit/s;并且该器件结构尺寸仅为13 μm×14 μm,易于集成。该异或逻辑结构中引入了二维光子晶体马赫-曾德尔干涉仪,使得光子晶体逻辑门结构的设计更加多样,并为二维光子晶体半加器与全加器的设计提供了基础,具有重要的研究意义。     

A New Coplanar Design of Multiplier Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) nanotechnology is emerging as a replacement technique for maintaining increasing microprocessor performance and it yields small size, high speed, and low power consumption. On the other hand, a multiplier is a circuit that multiplies two binary values for performing sequential addition operations and accumulating the results. This type of circuit is the basic structural unit of many arithmetic logical units, digital signal processing, and communication system. The multiplier circuit contains some full adders that can perform add operations, so, it is very important that low-complexity full adders are used. Therefore, in this paper, a new 2 × 2 array multiplier circuit in QCA by employing an efficient structure of full adder is designed and implemented. This design is constructed using coplanar layouts and compared its performance with existing QCA multipliers. The operation and efficiency of the proposed structure have been confirmed using QCADesigner tool. The simulation results have demonstrated that the 2 × 2 multiplier leads to less cell count and area as the prime designing factors.

     

Optical arithmetic unit using bit-WDM

A novel arithmetic unit is proposed consisting of a pipelined optical ripple carry adder that adds two words with bits multiplexed by different wavelengths on a single fiber. The addition result is returned to a fiber bus in the same format as the incoming words. The corresponding operand bit pairs are split off the fiber using wavelength division demultiplexers. Full adders compute the sum for each bit pair and the carry from the next lower significant bit pair. The full adder uses couplers and NOT, NOR and novel XOR logic gates constructed using semiconductor optical amplifiers for gain and wavelength shifting.     

An Efficient Module for Full Adders in Quantum-dot Cellular Automata

Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective alternative to conventional CMOS-based integrated circuits. Modular design methodology in QCA domain has not been widely investigated. In this paper, an efficient module with fault tolerance is proposed, which can be employed to fabricate three-input and five-input majority gates that are the fundamental primitives for designing circuits in QCA. With cells omission in the versatile module, various logic gates will be achieved, such as Nand-Nor-Inverter (NNI) gate and And-Or-Inverter (AOI) gate. Moreover, in order to seek out an efficient full adder, five various QCA full adders are designed and exhaustively compared in terms of area, complexity, latency, reliability and power dissipation and also compared with existing fault-tolerant full adders. Two simulation tools, QCADesigner and QCAPro, are utilized in the waveform simulations for verifying the correctness of proposed circuits and power consumption, respectively. The analysis results reveal that full adder V has significant improvements in contrast to its counterparts with above criteria. To test the practicability of full adder V, multi-bit adders will be designed in single-layer and compared with previous adders in terms of area, complexity and QCA cost, which proves the merits of our work.     

All-optical reconfigurable logic operations with the help of terahertz optical asymmetric demultiplexer

An all-optical reconfigurable logic operation essentially constitutes a key technology for avoiding complex and speed limited optoelectronics conversions and performing various processing tasks. All-optical reconfigurable logic operations with the help of terahertz optical asymmetric demultiplexer (TOAD) is proposed and described. The paper describes the all-optical reconfigurable logic operations using a set of all-optical multiplexer and optical switches. We have tried to exploit the advantages of TOAD-based switch to design an integrated all-optical circuit which can perform the different logic operations AND, XOR, NOR and NOT. Numerical simulation confirming described methods is given in this paper.     

A Power-Efficient Single Layer Full Adder Design in Field-Coupled QCA Nanocomputing

As an emerging technology device, Quantum-dot cellular automata (QCA) may be a suitable substitute for traditional semiconductor transistor technology. Arithmetic logic unit in field-coupled QCA has been also studied extensively in recent year. In this paper, the new low-power Exclusive-OR gate is presented, which is mainly based on QCA cellular leveled format. This Exclusive-OR gate can be used to design various useful QCA circuits. By using this gate, we design and implement a novel full adder circuit with low dissipation. The circuit is designed using only 45 normal cells in a single layer without crossover. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The operation of the proposed circuit has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared with previous designs in terms of power dissipation, cell-counts, area, latency and cost. The proposed full adder has the smallest area with less number of cells. And the total energy dissipation of our proposed full adder are only 0.05112 eV, 0.07454 eV and 0.10181 eV when tunneling energy levels are 0.5 Ek, 1 Ek and 1.5 Ek, respectively. The proposed single full adder also has the lowest total energy dissipation with a reduction of 20.94, 11.25 and 4.82% in 0.5 E_k, 1 E_k and 1.5 E_k tunneling energy levels, respectively when compared with the previous most power-efficient design.

     

Quantum Fourier Transform-Based Arithmetic Logic Unit on a Quantum Processor

This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two-input and four-input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform-based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft-core processor on a quantum processing unit.     

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.     

Parity checking and generating circuit with semiconductor optical amplifier in all-optical domain

In this paper, an all-optical parity checker and parity generator circuit is proposed in which SOA-MZI configuration is used to implement the XOR logic gate. This performance monitoring logic device is simulated at ultra high speed i.e. 120 GHz. Two logic circuits are proposed for parity generator, in one design inverter used to generate parity bit is implemented by the same additional XOR gate as inverter while in 2nd design inverter is implemented using XGM in SOA and thus number of SOA in 2nd design is reduced. ER ratio achieved in 1st case is 9.28 with maximum Q factor 73.39 and minimum BER 0 while in 2nd design it is 9.35 with maximum Q factor 8.41 and minimum BER 1.93e−17. ER ratio achieved in parity checker circuit is 32.54 with maximum Q factor 77.76 and minimum BER 0.     

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

     

Investigation of Deuterium Substitution Effects in a Polymer Membrane Using IR Fourier Spectrometry

Since last few decades optics has already proved its strong potentiality for conducting parallel logic, arithmetic and algebraic operations due to its super-fast speed in communication and computation. So many different logical and sequential operations using all optical frequency encoding technique have been proposed by several authors. Here, we have keened out all optical dibit representation technique, which has the advantages of high speed operation as well as reducing the bit error problem. Exploiting this phenomenon, we have proposed all optical frequency encoded dibit based XOR and XNOR logic gates using the optical switches like add/drop multiplexer (ADM) and reflected semiconductor optical amplifier (RSOA). Also the operations of these gates have been verified through proper simulation using MATLAB (R2008a).