Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

     

Design of Cost-Efficient QCA Reversible Circuits via Clock-Zone-Based Crossover

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel Reversible Gate is developed using QCA technology. Performance of the proposed gate is verified using thirteen standard three variables Boolean functions, which demonstrate from 14.3% to 42.8% superiority in term of gate counts obtained with other reversible gates. Proposed reversible gate requires switching and leakage energy dissipation of 0.168 eV and 0.271 eV, respectively, at 1.5 E_k energy level. The proposed gate uses 146 cells occupying only 0.14 μ m² area and then used to design a full adder. We use a coplanar QCA crossover architecture in the designs that uses non-adjacent clock zones for the two crossing wires. These designs have been realized with QCADesigner.     

A Power-Efficient Single Layer Full Adder Design in Field-Coupled QCA Nanocomputing

As an emerging technology device, Quantum-dot cellular automata (QCA) may be a suitable substitute for traditional semiconductor transistor technology. Arithmetic logic unit in field-coupled QCA has been also studied extensively in recent year. In this paper, the new low-power Exclusive-OR gate is presented, which is mainly based on QCA cellular leveled format. This Exclusive-OR gate can be used to design various useful QCA circuits. By using this gate, we design and implement a novel full adder circuit with low dissipation. The circuit is designed using only 45 normal cells in a single layer without crossover. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The operation of the proposed circuit has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared with previous designs in terms of power dissipation, cell-counts, area, latency and cost. The proposed full adder has the smallest area with less number of cells. And the total energy dissipation of our proposed full adder are only 0.05112 eV, 0.07454 eV and 0.10181 eV when tunneling energy levels are 0.5 Ek, 1 Ek and 1.5 Ek, respectively. The proposed single full adder also has the lowest total energy dissipation with a reduction of 20.94, 11.25 and 4.82% in 0.5 E_k, 1 E_k and 1.5 E_k tunneling energy levels, respectively when compared with the previous most power-efficient design.

     

An Efficient Module for Full Adders in Quantum-dot Cellular Automata

Quantum-dot cellular automata (QCA), a new computing paradigm at nanoscale, may be a prospective alternative to conventional CMOS-based integrated circuits. Modular design methodology in QCA domain has not been widely investigated. In this paper, an efficient module with fault tolerance is proposed, which can be employed to fabricate three-input and five-input majority gates that are the fundamental primitives for designing circuits in QCA. With cells omission in the versatile module, various logic gates will be achieved, such as Nand-Nor-Inverter (NNI) gate and And-Or-Inverter (AOI) gate. Moreover, in order to seek out an efficient full adder, five various QCA full adders are designed and exhaustively compared in terms of area, complexity, latency, reliability and power dissipation and also compared with existing fault-tolerant full adders. Two simulation tools, QCADesigner and QCAPro, are utilized in the waveform simulations for verifying the correctness of proposed circuits and power consumption, respectively. The analysis results reveal that full adder V has significant improvements in contrast to its counterparts with above criteria. To test the practicability of full adder V, multi-bit adders will be designed in single-layer and compared with previous adders in terms of area, complexity and QCA cost, which proves the merits of our work.     

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

     

Fault-Tolerant Design of a Shift Register at the Nanoscale Based on Quantum-dot Cellular Automata

Quantum-dot Cellular Automata (QCA) as a novel technology in the nanometer scale has been considered as one of the substitutes to CMOS technology. The QCA helps to create faster computers with lower power consumption. On the other hand, a shift register as one of the most important logical circuit in the digital systems consists of a line of latches. Also, the QCA-based designs have more advantages compared to the conventional CMOS designs. However, some deposition defects are possible to occur in the QCA-based designs, which have necessitated the fault-tolerant structures. Therefore, this paper aims to design an optimized 2-bit universal shift register based on QCA technology through the optimized multiplexer and D flip-flop. This paper studies the functionality and the fault tolerance of the proposed universal shift register in the presence of the QCA deposition faults. The structure of the 2-bit universal register is extendable to 4-bit, 8-bit and higher. The proposed design has better performance regarding fault tolerant, complexity and area consumption compared to the current designs based on the achieved results via QCADesigner.     

Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata

Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.     

Optimization Approaches for Designing a Novel 4-Bit Reversible Comparator

Reversible logic is a new rapidly developed research field in recent years, which has been receiving much attention for calculating with minimizing the energy consumption. This paper constructs a 4×4 new reversible gate called ZRQ gate to build quantum adder and subtraction. Meanwhile, a novel 1-bit reversible comparator by using the proposed ZRQC module on the basis of ZRQ gate is proposed as the minimum number of reversible gates and quantum costs. In addition, this paper presents a novel 4-bit reversible comparator based on the 1-bit reversible comparator. One of the vital important for optimizing reversible logic is to design reversible logic circuits with the minimum number of parameters. The proposed reversible comparators in this paper can obtain superiority in terms of the number of reversible gates, input constants, garbage outputs, unit delays and quantum costs compared with the existed circuits. Finally, MATLAB simulation software is used to test and verify the correctness of the proposed 4-bit reversible comparator.     

Design of Improved Arithmetic Logic Unit in Quantum-Dot Cellular Automata

The quantum-dot cellular automata (QCA) can be replaced to overcome the limitation of CMOS technology. An arithmetic logic unit (ALU) is a basic structure of any computer devices. In this paper, design of improved single-bit arithmetic logic unit in quantum dot cellular automata is presented. The proposed structure for ALU has AND, OR, XOR and ADD operations. A unique 2:1 multiplexer, an ultra-efficient two-input XOR and a low complexity full adder are used in the proposed structure. Also, an extended design of this structure is provided for two-bit ALU in this paper. The proposed structure of ALU is simulated by QCADesigner and simulation result is evaluated. Evaluation results show that the proposed design has best performance in terms of area, complexity and delay compared to the previous designs.     

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.     

Designing a New 4:2 Compressor Using an Efficient Multi-Layer Full-Adder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is novel prominent nanotechnology. It promises a substitution to Complementary Metal–Oxide–Semiconductor (CMOS) technology with a higher scale integration, smaller size, faster speed, higher switching frequency, and lower power consumption. It also causes digital circuits to be schematized with incredible velocity and density. The full adder, compressor, and multiplier circuits are the basic units in the QCA technology. Compressors are an important class of arithmetic circuits, and researchers can use quantum compressors in the structure of complex systems. In this paper, first, a novel three-input multi-layer full-adder in QCA technology is designed, and based on it, a new multi-layer 4:2 compressor is presented. The proposed QCA-based full-adder and compressor uses an XOR gate. The proposed design offers good performance regarding the delay, area size, and cell number comparing to the existing ones. Also, in this gate, the output signal is not enclosed, and we can use it easily. The accuracy of the suggested circuits has been assessed with the utilization of QCADesigner 2.0.3. The results show that the proposed 4:2 compressor architecture utilizes 75 cell and 1.25 clock phases, which are efficient than other designs.

     

Quantum legitimacy of reversible gate and a new design of multiplier based on R gate

Quantum full adders play a key role in the design of quantum computers. The efficiency of a quantum adder directly determines the speed of the quantum computer, and its complexity is closely related to the difficulty and the cost of building a quantum computer. The existed full adder based on R gate is a great design but it is not suitable to construct a quantum multiplier. We show the quantum legitimacy of some common reversible gates, then use R gate to propose a new design of a quantum full adder. We utilize the new designed quantum full adder to optimize the quantum multiplier which is based on R gate. It is shown that the new designed one can be optimized by a local optimization rule so that it will have lower quantum cost than before.     

Novel Efficient Circuit Design for Multilayer QCA RCA

The novel emerging technology, QCA technology, is a candidate for replacing CMOS technology. Full Adder (FA) circuits are also widely used circuits in arithmetic circuits design. In this paper, two new multilayer QCA architectures are presented: one-bit FA and 4-bit Ripple Carry Adder (RCA). The designed one-bit multilayer FA architecture is based on a new XOR gate architecture. The designed 4-bit multilayer QCA RCA is also developed based on the designed one-bit multilayer QCA FA. The functionality of the designed architectures are verified using QCADesigner tool. The results indicate that the designed architecture for 4-bit multilayer QCA RCA requires 5 clock phases, 125 QCA cells, and 0.17 μm² area. The comparison results confirm that the designed architectures provide improvements compared with other adder architectures in terms of cost, cell count, and area.

     

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.     

New Design for Quantum Dots Cellular Automata to obtain Fault Tolerant Logic Gates

In this paper, we analyze fault tolerance properties of the Majority Gate, as the main logic gate for implementation with Quantum dots Cellular Automata (QCA), in terms of fabrication defect. Our results demonstrate the poor fault tolerance properties of the conventional design of Majority Gate and thus the difficulty in its practical application. We propose a new approach to the design of QCA-based Majority Gate by considering two-dimensional arrays of QCA cells rather than a single cell for the design of such a gate. We analyze fault tolerance properties of such Block Majority Gates in terms of inputs misalignment and irregularity and defect (missing cells) in assembly of the array. We present simulation results based on semiconductor implementation of QCA with an intermediate dimensional dot of about 5 nm in size as opposed to magnetic dots of greater than 100 nm or molecular dots of 2–5Å. Our results clearly demonstrate the superior fault tolerance properties of the Block Majority Gate and its greater potential for a practical realization. We also show the possibility of designing fault tolerant QCA circuits by using Block Majority Gates.     

RETRACTED ARTICLE: A New Design of 2-Bit Universal Shift Register Using Rotated Majority Gate Based on Quantum-Dot Cellular Automata Technology

Quantum-dot Cellular Automata (QCA) is emerging nanotechnology that can represent binary information using quantum cells without current flows. It is known as a promising alternative of Complementary Metal–Oxide Semiconductor (CMOS) to solve its drawbacks. On the other hand, the shift register is one of the most widely used practical devices in digital systems. Also, QCA has the potential to achieve attractive features than transistor-based technology. However, very small-scale and Nano-fabrication limits impose a hurdle to the design of QCA-based circuits and necessitate for fault-tolerant analysis is appeared. Therefore, the aim of this paper is to design and simulate an optimized a D-flip-flop (as the main element of the shift register) based on QCA technology, which is extended to design an optimized 2-bit universal shift register. This paper evaluates the performance of the designed shift register in the presence of the QCA fault. Collected results using QCADesigner tool demonstrate the fault-tolerant feature of the proposed design with minimum clocking and area consumption.

     

A New Coplanar Design of Multiplier Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) nanotechnology is emerging as a replacement technique for maintaining increasing microprocessor performance and it yields small size, high speed, and low power consumption. On the other hand, a multiplier is a circuit that multiplies two binary values for performing sequential addition operations and accumulating the results. This type of circuit is the basic structural unit of many arithmetic logical units, digital signal processing, and communication system. The multiplier circuit contains some full adders that can perform add operations, so, it is very important that low-complexity full adders are used. Therefore, in this paper, a new 2 × 2 array multiplier circuit in QCA by employing an efficient structure of full adder is designed and implemented. This design is constructed using coplanar layouts and compared its performance with existing QCA multipliers. The operation and efficiency of the proposed structure have been confirmed using QCADesigner tool. The simulation results have demonstrated that the 2 × 2 multiplier leads to less cell count and area as the prime designing factors.

     

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal–Oxide–Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.     

二维光子晶体全光异或门的设计及研究

分析了二维光子晶体马赫-曾德尔干涉仪的传输特性,将二维光子晶体波导、环形腔和马赫-曾德尔干涉仪有效结合,提出了一种基于二维光子晶体马赫-曾德尔干涉仪的异或门设计。用平面波展开法分析二维光子晶体能带结构,并用时域有限差分法验证光信号在该器件中的电场稳态分布。结果表明,该结构能够实现异或逻辑,且具有高逻辑对比度7.88 dB,快速响应周期0.388 ps和高传输速率7.87 Tbit/s;并且该器件结构尺寸仅为13 μm×14 μm,易于集成。该异或逻辑结构中引入了二维光子晶体马赫-曾德尔干涉仪,使得光子晶体逻辑门结构的设计更加多样,并为二维光子晶体半加器与全加器的设计提供了基础,具有重要的研究意义。     

Mach-Zehnder interferometer-based all-optical reversible logic gate

In recent years, reversible logic has emerged as a promising computing paradigm having application in low-power CMOS, quantum computing, nanotechnology and optical computing. Optical logic gates have the potential to work at macroscopic (light pulses carry information), or quantum (single photons carry information) levels with great efficiency. However, relatively little has been published on designing reversible logic circuits in all-optical domain. In this paper, we propose and design a novel scheme of Toffoli and Feynman gates in all-optical domain. We have described their principle of operations and used a theoretical model to assist this task, finally confirming through numerical simulations. Semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometer (MZI) can play a significant role in this field of ultra-fast all-optical signal processing. The all-optical reversible circuits presented in this paper will be useful to perform different arithmetic (full adder, BCD adder) and logical (realization of Boolean function) operations in the domain of reversible logic-based information processing.