一种用于3D NAND存储器的高压生成电路

设计了一种应用于3D NAND 存储器的高压生成电路,包括振荡器、时钟生成电路、新型电荷泵及反馈环路。与传统的电荷泵相比,新型电荷泵消除了阈值电压损失与衬底偏置效应,提高了升压效率。通过控制时钟的电压幅度来调节输出电压,减小了输出电压纹波。电路在0.32 μm CMOS工艺模型下进行了仿真验证。结果表明,在3.3 V工作电压下,该电路稳定输出15 V的高压,上升时间为3.4 μs,纹波大小为82 mV,最大升压效率可达到76%。该高压生成电路在各项性能指标之间取得了平衡,其突出的综合性能能满足3D NAND存储器的工作需求。     

Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application

A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application.     

Analysis of 3D NAND technologies and comparison between charge-trap-based and floating-gate-based flash devices

NAND flash chips have been innovated from two-dimension (2D) design which is based on planar NAND cells to three-dimension (3D) design which is based on vertical NAND cells. Two types of NAND flash technologies–charge-trap (CT) and floating-gate (FG) are presented in this paper to introduce NAND flash designs in detail. The physical characteristics of CT-based and FG-based 3D NAND flashes are analyzed. Moreover, the advantages and disadvantages of these two technologies in architecture, manufacture, interference and reliability are studied and compared.     

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.     

一种高效率的适合于低功耗应用的电荷泵电路

设计实现了一种高效率的电荷泵电路。利用电容和晶体管对电荷传输开关进行偏置来消除开关管阈值电压的影响。同时,通过对开关管的的衬底进行动态的偏置使得在电荷传输期间当开关管打开时其阈值电压较低,在开关管关断时其阈值电压较高。该电荷泵电路的效率得到了提高。基于0.18μm,3.3V标准CMOS工艺实现了该电路。在每级电容为0.5pF,时钟频率为780KHz,电源电压为2V的情况下,测得的8级电荷泵的输出电压为9.8V。电荷泵电路和时钟驱动电路从电源处总共消耗了2.9μA的电流。该电荷泵电路适合于低功耗的应用。     

3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture

A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application.     

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.     

新型多位非均匀沟道电荷俘获型存储器及新型虚拟源端的NAND阵列结构

为了解决传统多位存储NAND型存储器中位与位互相干扰的问题,本文提出了一种新型的用于多位存储的非均匀沟道电荷俘获型存储器及新型NAND结构。该器件能够很好地抑制SBE效应从而提供3比特/单元的存储能力。由于n-缓冲区的存在,由SBE效应导致的阈值电压漂移能够减小到400mV,在3比特/单元的存储能力下最小阈值电压窗口可以达到750mV。本器件还引入了富硅氮氧化硅层最为电荷俘获层,从而很好地提高了器件的电荷保持特性。     

Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array

In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device,this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory(NUC-CTM) device with virtual-source NAND-type array architecture,which can effectively restrain the second-bit effect(SBE) and provide 3-bit per cell capability.Owing to the n~- buffer region,the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between ...     

基于QC-LDPC码的空间CCD图像NAND闪存存储纠错

为了提高空间CCD相机图像NAND闪存存储可靠性,提出一种基于QC-LDPC码的NAND闪存纠错算法。首先,分析了NAND闪存纠错信道模型;然后,根据闪存特点提出了一种基于QC-LPDC(1056,1024)码的NAND闪存纠错算法,为了加快编码效率提出了校验矩阵构造和高效编码方法,设计的校验阵均是0和1,只有移位和加法运算,非常适合硬件实现;最后,使用地面检测设备对闪存纠错算法进行了试验验证。结果表明,闪存纠错算法能快速稳定、可靠地工作,计算复杂度比较低,算法复杂度仅具为O(N);算法纠错能力高,误码比(BER)为10-6时,本文算法比RS码多0.47dB编码增益;使用65nm CMOS单元库,系统工作频率为250MHz时解码器数据吞吐率达到7.2Gbps;低误码平层,在误比特率为10-8时未出现误码平层。本文的NAND闪存纠错算法满足了空间相机图像存储系统的应用。     

适于空间图像闪存阵列的非与闪存控制器

提出一种适于空间应用的非与(NAND,not and)闪存控制器。首先,分析了空间相机存储图像的要求,说明了闪存控制器结构的特点。接着,分析了闪存数据存储差错的机理,针对闪存结构组织特点提出了一种基于BCH(Bose-Chaudhuri-Hocquenghem,2108,2048,5)码的闪存纠错算法。然后,对传统BCH编码器进行了改进,提出了一种8bit并行蝶形阵列处理机制。最后,使用地面检测设备对闪存控制器进行了试验验证。结果表明,闪存控制器能快速稳定、可靠地工作,在闪存单页2Kbt/page下可以纠正40bit错误,在相机正常工作行频为2.5kHz下拍摄图像时4级流水线闪存连续写入速度达到133Mbit/s,可以满足空间相机图像存储系统的应用。     

一款新型电荷泵功率管驱动电路

提出了一款新型功率管驱动电路。P沟道功率管驱动电路加入了防死锁模块防止了死锁的出现,提高了瞬态响应;N沟道功率管驱动电路加入了附加的充电支路,提高了驱动能力和瞬态响应。整个电路基于0.6μm BCD工艺,在Cadence Spectre下仿真。和传统的功率管驱动电路相比,新的P沟道功率管驱动电路的上升时间由60ns减少到14ns,下降时间由240ns减少到30ns,并且功耗从2mW减少到1mW;新的N沟道功率管驱动电路的上升时间由360ns减少到27ns,功耗从1.1mW减少到0.8mW。     

An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC

in a 0.18μm low/mid/high mixed-voltage CMOS process.     

用于TFT-LCD驱动芯片的省面积高效率内置电荷泵

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC-DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump＇s power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.     

A novel charge pump drive circuit for power MOSFETs

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.     

闪存BCH译码器并行钱搜索的研究与改进

钱搜索是与非型闪速(NAND flash)存储器中BCH译 码器的重要组成部分,并行钱搜索延迟较小并可高速运行,但过高的复杂度制约了其的应用 。为了降低并行钱搜索的复杂度,提 出一种并行钱搜索的改进和优化方法。首先对传统并行钱搜索以及有关文献进行了分析和研 究;然后对公共子表达式的搜索范 围进行了扩展,并合并了相关计算;最后对迭代匹配算法进行了改进,提出一种基于二维搜 索的改进迭代匹配算法。实验结果 表明,本文方法取得了较好的优化效果,有效地降低了并行钱搜索的复杂度;在对BCH(2047,1926,1)的 32bit并行钱搜索 优化后,与传统并行钱搜索以及有关文献的两种并行钱搜索相比,本文方法的 优化率分别达 到了85.4%、38.7%和29.2%,并可以更好地适应不同并行度和不同纠错能力的并行钱搜索结构。     

三维闪存中基于钨互连的空气隙结构的制备工艺

将空气隙应用于逻辑器件后段金属互连线中可以有效降低互连线间的寄生电容,提升电路信号传输速度,但制备过程仍具有一定的困难。基于三维闪存(3D NAND)中后段(BEOL)W的自对准双重图形化(SADP)工艺,利用湿法刻蚀的方法在W化学机械平坦化(CMP)之后去除SiO_2介质层,然后再利用化学气相淀积(CVD)法淀积一层台阶覆盖率较低的介质在金属互连线层内形成空气隙。采用空气隙结构代替原来的SiO_2介质层可降低约37.4%的寄生电容,且薄膜的台阶覆盖率会进一步降低电容。TCAD仿真和电性能测试结果表明,采用该方法制备的空气隙结构可降低互连延迟。     

A 1.0 V power supply, 9.3 GB/s write speed, Single-Cell Self-Boost program scheme for high performance ferroelectric NAND flash SSD

A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0 V power supply operation in Ferroelectric (Fe-) NAND flash memories. The proposed SCSB scheme only self-boosts the channel voltage of the cell to which the program voltage V_PGM is applied in the program-inhibit NAND string. The program disturb is well suppressed at the 1.0 V power supply voltage in the proposed program scheme. The power consumption of the Fe-NAND at V_CC = 1.0 V decreases by 86% compared with the conventional floating gate (FG-) NAND at V_CC = 1.8 V without the degradation of the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.7 times and the 9.3 GB/s write throughput of the Fe-NAND SSD is achieved for an enterprise application.     

三维圆柱形电荷俘获存储器件的继续微缩对其性能的影响

本文详细地研究了关键尺寸的继续微缩对三维圆柱形无结型电荷俘获存储器器件性能的影响。通过Sentaurus三维器件仿真器,我们对器件性能的主要评价指标进行了系统地研究,包括编程擦除速度和高温下的纵向电荷损失及横向电荷扩散。沟道半径的继续微缩有利于操作速度的提升,但使得纵向电荷损失, 尤其是通过阻挡层的纵向电荷损失,变得越来越严重。栅极长度的继续微缩在降低操作速度的同时将导致俘获电荷有更为严重的横向扩散。栅间长度的继续微缩对于邻近器件之间的相互干扰有决定性作用,对于特定的工作温度及条件其值需谨慎优化。此外,栅堆栈的形状也是影响电荷横向扩散特性的重要因素。研究结果为高密度及高可靠性三维集成优化提供了指导作用。     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.