An Improved Design of n-Bit Universal Reversible Gate Library

Reversible logic has been considered as an important solution to the power dissipation problem in the existing electronic devices. Many universal reversible libraries that include more than one type of gates have been proposed in the literature. This paper proposes a novel reversible n-bit gate that is proved to be universal for synthesizing reversible circuits. Reducing the reversible circuit synthesis problem to permutation group allows Schreier-Sims Algorithm for the strong generating set-finding problem to be used in the synthesize of reversible circuits using the proposed gate. A novel optimization rules will be proposed to further optimize the synthesized circuits in terms of the number of gates, the quantum cost and the utilization of library to achieve better results than that shown in the literature.

     

Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit

Reversible logic is emerging as a promising alternative for applications in low-power design and quantum computation in recent years due to its ability to reduce power dissipation, which is an important research area in low power VLSI and ULSI designs. Many important contributions have been made in the literatures towards the reversible implementations of arithmetic and logical structures; however, there have not been many efforts directed towards efficient approaches for designing reversible Arithmetic Logic Unit (ALU). In this study, three efficient approaches are presented and their implementations in the design of reversible ALUs are demonstrated. Three new designs of reversible one-digit arithmetic logic unit for quantum arithmetic has been presented in this article. This paper provides explicit construction of reversible ALU effecting basic arithmetic operations with respect to the minimization of cost metrics. The architectures of the designs have been proposed in which each block is realized using elementary quantum logic gates. Then, reversible implementations of the proposed designs are analyzed and evaluated. The results demonstrate that the proposed designs are cost-effective compared with the existing counterparts. All the scales are in the NANO-metric area.     

Designing of Parity Preserving Reversible Vedic Multiplier

International Journal of Theoretical Physics - Reversible logic is used in designing low-power CMOS circuits, optical information processing, and quantum computing. Moreover, using parity...     

Optimization Approaches for Designing a Novel 4-Bit Reversible Comparator

Reversible logic is a new rapidly developed research field in recent years, which has been receiving much attention for calculating with minimizing the energy consumption. This paper constructs a 4×4 new reversible gate called ZRQ gate to build quantum adder and subtraction. Meanwhile, a novel 1-bit reversible comparator by using the proposed ZRQC module on the basis of ZRQ gate is proposed as the minimum number of reversible gates and quantum costs. In addition, this paper presents a novel 4-bit reversible comparator based on the 1-bit reversible comparator. One of the vital important for optimizing reversible logic is to design reversible logic circuits with the minimum number of parameters. The proposed reversible comparators in this paper can obtain superiority in terms of the number of reversible gates, input constants, garbage outputs, unit delays and quantum costs compared with the existed circuits. Finally, MATLAB simulation software is used to test and verify the correctness of the proposed 4-bit reversible comparator.     

Quaternary Quantum/Reversible Half-Adder,Full-Adder,Parallel Adder and Parallel Adder/Subtractor Circuits

Multiple valued quantum logic is a promising research area in quantum computing technology having several advantages over binary quantum logic. Adder circuits as well as subtractor circuits are the major components of various computational units in computers and other complex computational systems. In this paper, we propose a quaternary quantum reversible half-adder circuit using quaternary 1-qudit gates, 2-qudit Feynman and Muthukrishnan-Stroud gates. Then we propose a quaternary quantum reversible full adder and a quaternary quantum parallel adder circuit. In addition, we propose a quaternary quantum reversible parallel adder/subtractor circuit. The proposed designs are compared with existing designs and improvements in terms of hardware complexity, quantum cost, number of constant inputs and garbage outputs are reported.

     

Mach-Zehnder interferometer-based all-optical reversible logic gate

In recent years, reversible logic has emerged as a promising computing paradigm having application in low-power CMOS, quantum computing, nanotechnology and optical computing. Optical logic gates have the potential to work at macroscopic (light pulses carry information), or quantum (single photons carry information) levels with great efficiency. However, relatively little has been published on designing reversible logic circuits in all-optical domain. In this paper, we propose and design a novel scheme of Toffoli and Feynman gates in all-optical domain. We have described their principle of operations and used a theoretical model to assist this task, finally confirming through numerical simulations. Semiconductor optical amplifier (SOA)-based Mach-Zehnder interferometer (MZI) can play a significant role in this field of ultra-fast all-optical signal processing. The all-optical reversible circuits presented in this paper will be useful to perform different arithmetic (full adder, BCD adder) and logical (realization of Boolean function) operations in the domain of reversible logic-based information processing.     

Designing Nanoscale Counter Using Reversible Gate Based on Quantum-Dot Cellular Automata

Some new technologies such as Quantum-dot Cellular Automata (QCA) is suggested to solve the physical limits of the Complementary Metal-Oxide Semiconductor (CMOS) technology. The QCA as one of the novel technologies at nanoscale has potential applications in future computers. This technology has some advantages such as minimal size, high speed, low latency, and low power consumption. As a result, it is used for creating all varieties of memory. Counter circuits as one of the important circuits in the digital systems are composed of some latches, which are connected to each other in series and actually they count input pulses in the circuit. On the other hand, the reversible computations are very important because of their ability in reducing energy in nanometer circuits. Improving the energy efficiency, increasing the speed of nanometer circuits, increasing the portability of system, making smaller components of the circuit in a nuclear size and reducing the power consumption are considered as the usage of reversible logic. Therefore, this paper aims to design a two-bit reversible counter that is optimized on the basis of QCA using an improved reversible gate. The proposed reversible structure of 2-bit counter can be increased to 3-bit, 4-bit and more. The advantages of the proposed design have been shown using QCADesigner in terms of the delay in comparison with previous circuits.     

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

     

Expectation functionals of observables and counters

A discussion of properties, counters and observables in the framework of a quantum logic is given.We prove the following theorem: Let (P,?,′) be a quantum logic with a strong property (convex subset of states) M. If every M-detectable property (exposed face of M) is detected (exposed) by an expectational counter then every state belonging to M is completely additive.From this result we draw several important conclusions.     

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.     

Quantum Circuit Synthesis using a New Quantum Logic Gate Library of NCV Quantum Gates

Since Controlled-Square-Root-of-NOT (CV, CV^?) gates are not permutative quantum gates, many existing methods cannot effectively synthesize optimal 3-qubit circuits directly using the NOT, CNOT, Controlled-Square-Root-of-NOT quantum gate library (NCV), and the key of effective methods is the mapping of NCV gates to four-valued quantum gates. Firstly, we use NCV gates to create the new quantum logic gate library, which can be directly used to get the solutions with smaller quantum costs efficiently. Further, we present a novel generic method which quickly and directly constructs this new optimal quantum logic gate library using CNOT and Controlled-Square-Root-of-NOT gates. Finally, we present several encouraging experiments using these new permutative gates, and give a careful analysis of the method, which introduces a new idea to quantum circuit synthesis.     

Realization of Quantum Circuits in Fock Space

In this letter, by using the method we offered in our paper [L. Ma and Y.D. Zhang, Commun. Theor. Phys. (Beijing, China) 36 (2001) 119], some extended quantum logic gates, such as quantum counter, quantum adder, are studied and their expressions are given. It may be useful for us to study the more complicated quantum logic circuits deeply.     

Optically implementable designs of reversible sequential devices

We have proposed some new designs of reversible sequential circuits using NCT gate library and compared them with the earlier proposals. It has been shown that the present proposals have lower gate complexities and lower number of garbage bits compared to the earlier proposals. We have addressed some conceptual issues related to the feedback and the choice of gate library. Further it is shown that the proposed quantum / reversible circuits can be implemented optically.     

A quantum circuit design of AES requiring fewer quantum qubits and gate operations

Advanced Encryption Standard (AES) is one of the most widely used block ciphers nowadays, and has been established as an encryption standard in 2001. Here we design AES-128 and the sample-AES (S-AES) quantum circuits for deciphering. In the quantum circuit of AES-128, we perform an affine transformation for the SubBytes part to solve the problem that the initial state of the output qubits in SubBytes is not the |0>^⊗8 state. After that, we are able to encode the new round sub-key on the qubits encoding the previous round sub-key, and this improvement reduces the number of qubits used by 224 compared with Langenberg et al.’s implementation. For S-AES, a complete quantum circuit is presented with only 48 qubits, which is already within the reach of existing noisy intermediate-scale quantum computers.     

On Design of Parity Preserving Reversible Adder Circuits

In this paper novel parity preserving reversible logic blocks are presented and verified. Then, we present cost-effective parity preserving reversible implementations of Full Adder, 4:2 Compressor, Binary to BCD converter, and BCD adder using these blocks. The proposed parity preserving reversible BCD adder is designed by cascading the presented 4-digit parity preserving reversible Full Adder and a parity preserving reversible Binary to BCD Converter. In this design, instead of realizing the detection and correction unit, we design a Binary to BCD converter that its inputs are the output of parity preserving binary adder, and its output is a parity preserving BCD digit. In addition, several theorems on the numbers of garbage outputs, constant inputs, quantum cost and delay of the designs have been presented to show its optimality. In the presented circuits, the delay and the quantum cost are reduced by deriving designs based on the proposed parity preserving reversible blocks. The advantages of the proposed designs over the existing ones are quantitatively described and analysed. All the scales are in the Nano-metric area.     

Quantum Fourier Transform-Based Arithmetic Logic Unit on a Quantum Processor

This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two-input and four-input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform-based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft-core processor on a quantum processing unit.     

Cost Optimization Technique for Quantum Circuits

In this paper, an attempt is made to present a method of quantum cost minimization or optimization technique for quantum reversible circuits using proposed merger rules in Exclusive Sum of Product (ESOP) method. These modified ESOP methods are used to minimize the quantum circuits. We found that the quantum cost is drastically decreased than the previous ESOP method. It will be easy to find the quantum cost and quantum gate optimized quantum circuits implementation. It will also reduce quantum error while the quantum circuit is executed in real quantum processor.

     

Counters Designs with Minimum Number of Cells and Area in the Quantum-Dot Cellular Automata Technology

The quantum-dot cellular automata (QCA) were highly regarded due to its high operating frequency and significantly low power consumption. One of the most useful circuits in processors architecture is counter. This paper presents effective designs and arrangement of QCA based counter-circuits. In this study new counter circuits in QCA technology are designed and precise simulation are done using the QCADesigner. Three, four and five bits counters are proposed in this paper in QCA technology. A comparison is made between the past and recent designs to illustrate which method is better and more efficient in terms of area, complexity, number of cells, and delay. For example, the proposed three bit shift register has 174 quantum cells, 0.2μm² occupied area and three QCA clock cycles delay.

     

III–V quantum devices and circuits based on nanoscale Schottky gate control of hexagonal quantum wire networks

The concept, the present status, key issues and future prospects of a novel hexagonal binary decision diagram (BDD) quantum circuit approach for III–V quantum large-scale integrated circuits (QLSIs) are presented and discussed. In this approach, the BDD logic circuits are implemented on III–V semiconductor-based hexagonal nanowire networks controlled by nanoscale Schottky gates. The hexagonal BDD QLSIs can operate at delay-power products near the quantum limit in the quantum regime as well as in the many-electron classical regime. To demonstrate the feasibility of the present approach, GaAs Schottky wrap gate (WPG)-based single-electron BDD node devices and their integrated circuits were fabricated and their proper operations were confirmed. Selectively grown InGaAs sub-10 nm quantum wires and their hexagonal networks have been investigated to form high-density hexagonal BDD QLSIs operating in the quantum regime at room temperature.