Effect of Reverse Substrate Bias on Degradation of Ultra-Thin Gate-Oxide n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors under Different Stress Modes

Degradation of ultra-thin gate-oxide n-channel metal-oxide-semiconductor field-effect transistors with the halo structure has been studied under different stress modes with a reverse substrate bias. The device degradation under the same stress mode with different reverse substrate voltages has been characterized by monitoring the substrate current in a stressing process, which follows a simple power law. When the gate voltage is less than the critical value, the device degradation will first decrease and then increase with the increasing reverse substrate voltage, otherwise, the device degradation will increase continuously. The critical value can be obtained by measuring the substrate current variation with the increases of reverse substrate voltage and gate voltage. The experimental results indicate that the stress mode with enhanced injection efficiency and smaller device degradation can be obtained when the gate voltage is less than the critical value with a proper reverse substrate voltage chosen.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.     

High-photosensitivity polymer thin-film transistors based on poly（3-hexylthiophene）

Polymer thin-film transistors(PTFTs) based on poly(3-hexylthiophene) are fabricated by the spin-coating process,and their photo-sensing characteristics are investigated under steady-state visible-light illumination.The photosensitivity of the device is strongly modulated by gate voltage under various illuminations.When the device is in the subthreshold operating mode,a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10 3 at an illumination intensity of 1200 lx,and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx.However,when the device is in the on-state operating mode,the photosensitivity is very low:only 1.88 at an illumination intensity of 1200 lx for a gate voltage of-20 V and a drain voltage of -20 V.The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light.The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.     

Actions of negative bias temperature instability (NBTI) and hot carriers in ultra-deep submicron p-channel metal——oxide——semiconductor field-effect transistors (PMOSFETs)

Hot carrier injection (HCI) at high temperatures and different values of gate bias V_g has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-stress-induced damage at V_g=V_d, where V_d is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different: the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal--oxide--semiconductor field-effect transistors (PMOSFETs). We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.     

Hot carrier injection degradation under dynamic stress

In this paper,we have studied hot carrier injection(HCI) under alternant stress.Under different stress modes,different degradations are obtained from the experiment results.The different alternate stresses can reduce or enhance the HC effect,which mainly depends on the latter condition of the stress cycle.In the stress mode A(DC stress with electron injection),the degradation keeps increasing.In the stress modes B(DC stress and then stress with the smallest gate injection) and C(DC stress and then stress with hole injection under V g = 0 V and V d = 1.8 V),recovery appears in the second stress period.And in the stress mode D(DC stress and then stress with hole injection under V g = 1.8 V and V d = 1.8 V),as the traps filled in by holes can be smaller or greater than the generated interface states,the continued degradation or recovery in different stress periods can be obtained.     

Characteristics of the transmission spectrum of the long period fiber gratings based on the coupling of core mode to the higher order cladding modes

The characteristics of the transmission spectrum of the Long-period fiber gratings (LPFGs) based on the coupling of core mode to a higher order cladding mode (HE mode) are investigated using the coupled mode theory. This kind of LPFGs is different from that based on the coupling of core mode to a lower order cladding mode because of the effect of the coupling of core mode to EH cladding mode. When the cladding mode order is higher, the coupling coefficients of core mode to HE and EH cladding modes are comparable and both of the propagation constants of HE and EH cladding modes approach, so the spectrum has an additional loss peak. The bandwidth of LPFG based on the coupling of core mode to different cladding mode differs greatly. With the change of the mode orders from lower to higher, the transmission spectrum changes from narrow to wide and more narrow.     

Single-mode low threshold current multi-hole vertical-cavity surface-emitting lasers

A multi-hole vertical-cavity surface-emitting laser(VCSEL) operating in stable single mode with a low threshold current was produced by introducing multi-leaf scallop holes on the top distributed Bragg-reflector of an oxidationconfined 850 nm VCSEL.The single-mode output power of 2.6 mW,threshold current of 0.6 mA,full width of half maximum lasing spectrum of less than 0.1 nm,side mode suppression ratio of 28.4 dB,and far-field divergence angle of about 10 are obtained.The effects of different hole depths on the optical characteristics are simulated and analysed,including far-field divergence,spectrum and lateral cavity mode.The single-mode performance of this multi-hole device is attributed to the large radiation loss from the inter-hole spacing and the scattering loss at the bottom of the holes,particularly for higher order modes.     

Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing(P/E) operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

AlGaN/GaN双异质结F注入增强型高电子迁移率晶体管

理论模拟了不同GaN沟道厚度的双异质结(AlGaN/GaN/AlGaN/GaN)材料对高电子迁移率晶体管(HEMT)特性的影响,并模拟了不同F注入剂量下用该材料制作的增强型器件的特性差异.采用双异质结材料,结合F注入工艺成功地研制出了较高正向阈值电压的增强型HEMT器件.实验研究了三种GaN沟道厚度制作的增强型器件直流特性的差异,与模拟结果进行了对比验证.采用降低的F注入等离子体功率,减小了等离子体处理工艺对器件沟道迁移率的损伤,研制出的器件未经高温退火即实现了较高的跨导和饱和电流特性.对14 nm GaN沟道厚度的器件进行了阈值电压温度稳定性和栅泄漏电流的比较研究,并且分析了双异质结器件的漏致势垒降低效应.     

电极布局对硅LED性能的影响

采用0.35μm双栅标准CMOS工艺设计和制备了叶型硅发光器件.叶型硅发光器件由3个楔型器件的组合而成,pn结结构为n阱/p+结.使用奥林巴斯IC显微镜测得了器件的显微图形,并对器件进行了电学特性测试.器件工作在雪崩击穿下,开启电压为8.8 V,能够发出黄色可见光;正向偏置下,器件开启电压为0.8 V.在与已经制备的楔...     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×10¹³ el/cm², a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×10¹⁴ el/cm² was observed.     

微腔有机电致发光白光器件设计及制作

用一种宽谱带材料Alq₃作为发光层,设计并制作白色有机微腔电致发光器件。器件结构:Glass/DBR/ITO(194 nm)/NPB(93 nm) /Alq₃(49 nm)/MgAg(150 nm),得到了位于蓝(488 nm)和红(612 nm)光区域的两个腔发射模式,并通过颜色匹配获得了白光。器件的最大电致发光亮度16 435 cd/m²,最大效率11.1 cd/A,典型亮度值100 cd/m²时的发光效率、电压、电流密度分别是9 cd/A,6 V和1.2 mA/cm²,CIE 色坐标为(0.32, 0.34)。在不同的驱动电压下,器件的发光颜色稳定,说明了微腔是一种制作白光OLED的有效结构。     

Process and device characteristics of self-assembled metal nano-crystal EEPROM

Metal nanocrystals self-assembled on gate tunneling oxide can be used to replace the conventional Si/Ge nanocrystals as the floating gate in EEPROM cells. We have demonstrated the successful use of Au and W with their respective process dependence and self-assembly characteristics. The new material options can potentially enhance the applicability and functionality of the nanocrystal EEPROM device. Implications on process integration, in particular the control oxide growth and overall thermal budget, are examined by microscopy, gate current injection and channel mobility monitoring. Charging by hot-carrier injection and control gate tunneling have both been observed by shifts in I–V characteristics. The electrostatic behavior of metal nanocrystals is similar to that of Si nanocrystals in terms of the asymmetrical threshold voltage on source–drain reversal after hot-carrier injection and the Coulomb blockade effects. The electrodynamic behavior is expected to be quite different due to the density of states, but further study is required for quantitative analysis.     

氧对IZO低压无结薄膜晶体管稳定性的影响

本文在室温下制备了无结结构的低压氧化铟锌薄膜晶体管, 并研究了氧分压对其稳定性的影响. 氧化铟锌无结薄膜晶体管具有迁移率高、结构新颖等优点, 然而氧化物沟道层易受氧、水分子等影响, 造成稳定性下降. 在室温下, 本文通过改变高纯氧流量制备氧化铟锌透明导电薄膜作为沟道层、源漏电极, 分析了氧压对于氧化物无结薄膜晶体管稳定性的影响. 为使晶体管在低电压(<2 V)下工作, 达到低压驱动效果, 本文采用具有双电层效应和栅电容大的二氧化硅纳米颗粒膜作为栅介质; 通过电学性能测试, 制备的晶体管工作电压仅为1 V、 开关电流比大于10⁶、亚阈值斜率小于100 mV/decade以及场效 应迁移率大于20 cm²/V·s. 实验研究表明, 通氧制备的氧化铟锌薄膜的电阻率会上升, 导致晶体管的阈值电压向正向漂移, 最终使晶体管的工作模式由耗尽型转变为增强型. 关键词： 薄膜晶体管 无结 氧化铟锌 氧分子