环扫电镜表征影响因素及芯片失效分析应用

对环境扫描电镜(ESEM)表征影响因素进行试验研究,根据半导体芯片的结构,进行成像参数优化,试验结果表明较为适合的优化参数为:腔室气压40Pa~80Pa,加速电压10kV~20kV.研究了裙散效应对能谱分析的影响,结果表明非分析区域元素含量与离能谱分析点的距离呈幂函数衰减,应证了文献报道的理论计算,对于能谱分析排除干扰元素有一定的参考意义.针对破坏性物理分析(DPA)试验中发现的塑封器件腐蚀缺陷,利用ESEM在优化参数下进行机理分析,结果表明玻璃钝化层裂纹是导致铝金属条被腐蚀的原因,而玻璃钝化层裂纹是由于器件材料性质不匹配,在热载荷条件下产生热应力而引起.这种表层缺陷极有可能因为镀膜而被掩盖,因此,利用ESEM检测半导体器件具有一定的必要性.     

Thermal resistance degradation of surface mounted power devices during thermal cycling

Backside scanning acoustic tomography (SCAT) images have been correlated to alloy morphology (cross-section) and composition data (stoichiometry) to model the Θ_JC degradation for surface mounted device packaged power ICs as a function of the temperature cycling range. We find that an appropriate setting of the die attach process can suppress needle-shaped Cu₃Sn in favor of roughly spheroid Cu₆Sn₅. We derived, from the degradation of the Θ_JC during thermal cycling stress tests with different temperature swings, an acceleration factor with the use of the Coffin–Manson law. The fit parameter q in this formula is 9.3 for the new improved setting of the die attach process when the high SO power (HSOP) package is used. The moisture sensitivity level has no significant influence. Finally, a maximum Θ_JC degradation of 0.33 K/W based on the normal distribution approach results in a minimum lifetime of 12 years. When a customer requires a maximum Θ_JC of 2.0 K/W at the end of life, 50 years can be guaranteed.     

Traveling heater method preparation and composition analysis of CdTe ingots

Large polycrystalline CdTe charges for the subsequent growth of CdTe and CdZnTe crystals were prepared by the traveling heater method (THM). The composition of the produced material was evaluated by vapor pressure scanning (VPS) analysis. Results from these analyses were instrumental in improving the THM CdTe compounding process. The optimization of THM process parameters, such as the compounding rate and the loading configuration of the synthesis crucible, led to the preparation of polycrystalline CdTe ingots with small deviation from stoichiometry. For five out of six analyzed samples, tellurium content between 50.0012 and 50.0043 at. pct was achieved, which is well below the tellurium saturation limit of the single-phase solid in equilibrium with the molten zone at the chosen THM process temperature.     

Qualification of plastic encapsulated microcircuits (PEM) for avionicsBased on ``Plastic Encapsulated Microcircuits (PEM) Qualification Testing'''', by J. A. Scalise, which appeared in the Proceedings of the 46th Electronic Components and Technology Conference, Orlando, FL, U.S.A., 28–31 May 1996, pp. 392–397. © 1996 IEEE.

Microcircuit package qualification testing is used to establish the reliability of integrated circuit processes and devices as they relate to part packaging. This paper presents the results of package qualification tests conducted on plastic encapsulated microcircuits (PEMs) and plastic discrete devices (diodes, transistors) used in avionics applications. Highly accelerated stress test (HAST) and temperature cycle (TC) test results, including part failure mechanisms and associated failure rates, are provided. A variety of plastic package styles and integrated circuit functions have been tested. Examples of package styles tested include small outline (SO), plastic leaded chip carrier (PLCC), thin small outline package (TSOP), plastic quad flat package (PQFP) and plastic dual-in-line (PDIP).Manufacturers' devices have been evaluated and various plastic compounds have been compared to determine which provide optimum reliability. The testing showed that package qualification performance of PEMs is affected by type of compound, passivation (including die coat) and die size. HAST failures are caused by moisture penetration of the package while temperature cycle failures result from coefficient of thermal expansion (CTE) mismatch effects.     

集成电路封装级失效及其定位

失效分析中有许多类型的封装级失效.由于封装材料限制或者无损检测要求,无法从外观直接观察到失效点,需要借助于设备进行失效定位才能快速、准确地进行分析.总结了集成电路封装级失效的几种常见失效机理和失效原因,提出三种有效的分析手段和分析方法进行失效定位:X射线检测、超声扫描声学显微镜以及热激光激发光致电阻变化(OBIRCH)技术,分别用于元器件结构观察、不同材料界面特性分析和键合损伤位置定位.从倒装芯片封装、陶瓷封装、塑料封装和金铝键合短路四个失效分析的实际案例出发,阐明三种封装级失效定位手段应用的领域、特点和局限性.结果表明在封装级失效中,通孔断裂开路、焊料桥连短路、键合损伤和界面分层等缺陷能够准确地被定位进而分析.