Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.     

Modeling Custom Digital Circuits for Test

Models meant for logic verification and simulation are often used for Automatic Test Pattern Generation (ATPG). For custom digital circuits, these models contain many tristate devices that tend to lower coverage for stuck-faults. Additionally, these tristate devices contribute to increased ATPG runtimes, fewer generated test sequences, and an overall lower test quality. The circuit under test is partitioned into channel connected sub-networks (CCSN) that consist of transistors that are connected at their source or drain terminals, except when these terminals are power, ground or primary inputs. Unlike other published work, algorithms presented in this paper analyze each CCSN in the context of its environment, thereby capturing the logical relationships among its input signals. Other algorithms presented include identification and modeling of embedded latches, clock generators and memory circuits. An abstract array model for memory that reduces the size of the model and increases simulation speed is also presented. When one specific feature of the algorithm was disabled, experimental results showed higher ATPG runtimes of about 35%, and an average decrease in fault coverage of around 15–20%. For the largest data cache, the memory modeling algorithm decreased the number of primitives from 1.23 million to 139 thousand.     

数字化时代的模拟集成电路

文章介绍了数字化时代对模拟集成电路提出的挑战。从模拟集成电路的广阔发展空间、稳步的市场增长、不断出现的产品性能新水平、技术发展新趋势、以及极大的市场潜力和大好的发展机遇等方面，说明模拟集成电路在数字化时代存在的意义以及模拟集成电路的发展前景。     

模拟集成电路仿真中的UDSM MOSFET建模

对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,重点分析了在模拟集成电路设计中较为流行的几种模型:BSIM3、EKV和SP2001模型,对其各自的优缺点进行了比较。结果表明,获得能够精确地预测高性能模拟系统的模型是很困难的;几种模型中,EKV模型在模拟集成电路的低功耗设计中具有一定的优势。     

模拟电路功能级仿真

多级仿真是当前电路ＣＡＤ主要研究方向之一。本文首先提出模拟电路的两种行为模型，接着提出电路频域行为模型自动建立方法，同时给出两种模型功能级仿真的实现算法，文章最后给出功能级仿真实例。     

Fault Simulation for Analog Circuits Under Parameter Variations

Analog integrated circuit testing and diagnosis is a very challenging problem. The inaccuracy of measurements, the infinite domain of possible values and the parameter deviations are among the major difficulties. During the process of optimizing production tests, Monte Carlo simulation is often needed due to parameter variations, but because of its expensive computational cost, it becomes the bottleneck of such a process. This paper describes a new technique to reduce the number of simulations required during analog fault simulation. This leads to the optimization of production tests subjected to parameter variations. In Section 1 a review of the state of the art is presented, Section 2 introduces the algorithm and describes the methodology of our approach. The results on CMOS 2-stage opamp and Fifth-order Low-pass switched-capacitor Filter are given in Sections 3 and conclusions in Section 4.     

模拟集成电路的发展动态

本文介绍了Ａ／Ｄ与Ｄ／Ａ转换器、超高速ＳＯＩ器件及电路、超高速双极电路、ＧｅＳｉ／Ｓｉ异质结器件和电路、智能功率等模拟集成电路的发展概况。     

A Manufacturing Process for Analog and Digital Gallium Arsenide Integrated Circuits

A process for manufacturing small-to-medium scale GaAs integrated circuits is described. Integrated FET's, diodes, resistors, thin-film capacitors, and inductors are used for monolithic integration of digital and analog circuits. Direct implantation of Si into >10/sup 5/ omega/spl dot/cm resistivity substrates produces n-layers with +-10-percent sheet resistance variation. A planar fabrication process featuring retained anneal cap (SiO/sub 2/), proton isolation, recessed Mo-Au gates, silicon nitride passivation, and a dual-level metal system with polyimide intermetal dielectric is described. Automated on-wafer testing at frequencies up to 4 GHz is introduced, and a calculator-controlled frequency domain test system described. Circuit yields for six different circuit designs are reported, and process defect densities are inferred.     

模拟/数字电路的协调设计

设备厂家正在应付有关模拟性在设备设计中发挥作用,这就是模 模拟性质的故障指的是电路中质的各种问题:为了抑制噪声而支 拟/ 数字电路协调设计—对于噪声模拟性质的行为所引发的电磁辐射付的元器件费用激增;购买的集成引发的故障等防患于未然。而且, 噪声、信号完整性、电源的抖动等电路达不到技术规格标明的性能避免芯片“黑盒子”化并发挥其性问题。在很短的开发周期内,设计等。在这当中,新型的设备设计工 能,削减开发成本又缩短开发周工程师要利用有限的成本制定出解程师正在成为模拟技术和数字技术…     

Analog Integrated Circuits and Signal Processing

Analog Integrated Circuits and Signal Processing -     

Protel 99SE仿真在模拟电子电路中的应用

Protel公司的大型软件Protel 99SE由于其功能完善、易于掌握和使用方便等特点,成为最为流行的电子设计自动化(EDA)工具.利用EDA仿真软件对电路进行辅助分析,可以优化电路设计,缩短设计周期.文中介绍了Protel 99SE仿真功能的特点,并通过实例说明了用Protel 99SE进行仿真分析的具体方法,简要介绍了如何设置参数和进行仿真操作.     

模拟集成电路的自动优化设计

本文主要论述模拟集成电路自动优化设计的算法——复合形法和统计重心移动法;介绍基于PSPICE电路分析程序的自动优化设计系统及其在对数视频放大器设计中的应用和实验结果。     

基于仿真和编码理论的数模混联电路故障诊断方法研究

数模混联电路的设计被广泛运用于各种电路系统。而模拟电路和数字电路在故障模式、测试方法上的显著差别给数模混联电路的测试带来了很大困难。基于对输出电平的16进制编码,将传统的故障字典法推广到可以诊断数模混联电路的新故障字典法。利用EDA的辅助分析,在PSpice仿真环境下,从故障建模、故障注入,到电路仿真,数据分析,再到建立故障字典以及故障诊断,建立了一套有效的基于仿真的数模混联电路的测试诊断方法。并给出了仿真实例,对数、模混联电路的故障诊断具有推广意义。     

Design Approaches to Field-Programmable Analog Integrated Circuits

The drive towards shorter design cycles for analog integrated circuits has given impetus to several developments in the area of Field-Programmable Analog Arrays (FPAAs). Various approaches have been taken in implementing structural and parametric programmability of analog circuits. Recent extensions of this work have married FPAAs to their digital counterparts (FPGAs) along with data conversion interfaces, to form Field-Programmable Mixed-Signal Arrays (FPMAs). This survey paper reviews work to date in the area of programmable analog and mixed-signal circuits. The body of work reviewed includes university and industrial research, commercial products and patents. A time-line of important achievements in the area is drawn, the status of various activities is summarized, and some directions for future research are suggested.     

模拟集成电路测试平台建设

简述了模拟集成电路(IC)测试平台的概念和特点、国内外模拟IC测试平台的发展动态及差距，对模拟IC测试平台的建设与发展提出了建议。     

低电压模拟集成电路设计技术

以电池供电的模拟或A／D混合电子产品的广泛使用，要求设计出低电压模拟电路，以降低整机的功耗。文章简要介绍了五种适合模拟电路结构的低电压设计技术，比较了它们的优缺点和应用范围。     

模拟集成电路中的保护电路分析

本文主要介绍了模拟集成电路中各种保护电路的工作原理,并对常见集成电路中的保护电路作了详细分析。     

数模混合信号的测试与仿真

VLSI的发展特别是SoC的出现，对混合信号测试的研究提出了紧迫的要求。结合系统级芯片的可测试性设计技术所面临的技术难点．本文着重讨论了目前现有的各种测试手段及其各自的特点。     

集成电路和微电子机械系统加工过程中的光刻工艺模拟

基于3D元胞自动机方法实现了影像成形、曝光、后烘和光刻胶刻蚀过程等集成电路和微电子机械系统加工过程中的光刻过程模拟模块的集成.模拟结果与已有实验结果一致,表明基于3D元胞自动机方法的后烘和光刻胶刻蚀模拟模块的有效性,这对于实现集成电路和微电子机械系统的器件级的工艺模拟具有一定的实用性.     

数模混合电路的PCB设计

高速PCB的设计中,数模混合电路的PCB设计中的干扰问题一直是一个难题。尤其模拟电路一般是信号的源头,能否正确接收和转换信号是PCB设计要考虑的重要因素。文章通过分析混合电路干扰产生的机理,结合设计实践,探讨了混合电路一般处理方法,并通过设计实例得到验证。