Study of stress induced leakage current by using high resolution measurements

A thorough characterization of stress-induced leakage currents (SILCs) for a IOnm-thick oxide, by using the floating-gate technique, is presented. The obtained current is modeled by a volume-limited conduction mechanism. Experimental and model suggest that SILC conduction mechanism is the same in thin as well as in thick oxides.     

Channel width dependence of AC stress on bulk nMOSFETs

Channel width dependence of AC stress was investigated. OFF-state stress generated negative interface traps, positive oxide charges, and neutral traps in the whole channel region. Comparison of drain currents of parasitic and main MOSFET during OFF-state indicates that more defects were generated on channel edge than near its center. During ON-state stress, electrons were dominantly trapped in the neutral traps near channel edge. These results cause degradation due to AC stress to become increasingly severe as W is scaled down. The operating voltage to guarantee 10-year lifetime decreased as width decreased. The above results show that electron trapping in neutral traps near the channel edge induce severe degradation on narrow nMOSFET during AC stress. Therefore, degradation of channel edge during AC stress is an importantly considered in narrow nMOSFET.     

Wavelength and line width measurement of optical sources with femtometre resolution

A new and very simple method for the wavelength and line width measurement of optical sources with a resolution in the femtometre range is presented. Our method is based on the amplification of a backscattered wave by a pump wave due to Brillouin scattering. It requires neither a fast photodiode nor a spectrum analyser of any kind.     

Influence of ARC capping layer on stress induced voiding in narrow AlCu metallisations

The influence of capping layer composition was examined in accelerated stress-migration performance of AlCu(0.5%) narrow stripe lines. Using resistance monitoring and Scanning Electron Microscopy, we determined that metallisation with bilayer Ti/TiN ARC top layer induced more stress voiding than metallisation with single TiN ARC layer. These experimental results are discussed on the basis of a void growth mechanism provided by diffusion at the interface between AlCu and ARC top layer.     

Dynamics of electromigration induced void/hillock growth and precipitation/dissolution of addition elements studied by in-situ scanning electron microscopy resistance measurements

In the present paper it has been shown that the in-situ SEM resistance measurement technique is a powerful technique to study the dynamics of void/hillock growth and precipitation/dissolution of addition elements in a metal line submitted to a temperature/current stress. The power of the in-situ SEM resistance measurement technique is shown with the first results on Al1wt.%Si0.5wt.%Cu metal lines. During the electromigration experiment, performed in a SEM equipped with a heating stage, back scattered electron images are taken continuously over the entire length of the metal line monitoring a.o. the growth, shape variation and motion of voids/hillocks. The dissolution and motion of Al₂Cu precipitates in the Al1wt.%Si0.5wt.%Cu metal lines can also be monitored since the precipitates appear in the BSE mode as white objects. By comparing the observed electrical resistance drift results with the corresponding SEM micrographs it can be concluded that the resistance changes in the current stressed metal lines are mainly induced by geometrical changes.     

The kinetics of the early stages of electromigration and concurrent temperature induced processes in thin film metallisations studied by means of an in-situ high resolution resistometric technique

Compared with traditional test techniques, the in-situ high resolution resistometric technique allows a sensitive monitoring of thin film metallisations submitted to ’realistic’ current stress levels and reveals the occurrence of distinct reversible and irreversible processes. A review is provided of the processes observed in metallisations submitted to three regions of current stress: no current stress, low current density stress (j<0.5 MA/cm²) and ‘high’ current density stress (j>0.5 MA/cm²). Discarding the contributions of the concurrent, temperature induced, masking mechanisms results in an accurate observation of the kinetics of the early stages of electromigration, revealing fundamental features such as incubation time, subsequent linear resistance increase and current and temperature dependence.     

电镀铜厚差异对线宽的影响大小

本文针对电镀不均造成精细线路制作困难的问题,试验分析了不同电镀铜厚、不同最小间距板的线宽过蚀量,推算确定了不同电镀铜厚差异下的线宽大小差异值;并能根据线宽差异值反推出电镀铜厚差异的控制范围,为相关的生产指导和品质判定提供有价值、方便快捷的方法。     

The dependence of carrier lifetime on spectral width in multimode semiconductor lasers

Comprehensive measurements of the dependence of the carrier lifetime, eye pattern, and power penalty on the spectral width in multimode semiconductor lasers for a gigabit lightwave transmission system are presented. The results show that the carrier lifetime, eye pattern, and power penalty caused by mode partition noise (MPN) are strongly dependent on the source spectral width. The lasers with shorter carrier lifetimes exhibit a narrow spectral width, and hence show less MPN, a better eye opening, and a lower power penalty. A theoretical calculation of the MPN-induced power penalty is in good agreement with the measured system penalties. The likely cause for narrow spectral width with shorter carrier lifetime of the lasers is due to the smaller linewidth enhancement factor a caused by a higher doping concentration in the lasers.     

CMOS反相器在高功率微波下闩锁效应的温度影响

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.     

The effect of die attach voiding on the thermal resistance of chip level packages

The presence of voids in the die bond region is known to adversely affect the thermal resistance of the packaged chip-level device. Unfortunately, such voids are easily formed in the solder layer during manufacturing, and are found to nucleate, grow and coalesce with thermal cycling. Although the relationship between package thermal resistance and voids has been examined extensively, little data exist concerning the precise effects of void size, configuration and position. The present study allows the experimental investigation of these effects through application of an innovative experimental technique that carefully controls void geometry and distribution. The results show that for small, random voids, the thermal resistance, θ_jc, increases linearly with void volume percentage, V_%, according to the equation θ_jc = 0.007V + 1.4987, and for large, contiguous voids the increase follows the exponential relationship, θ_jc = 1.427e^0.015V. At 73% voiding, θ_jc was found to increase 30% and 200% for random and contiguous voids, respectively.     

Interface and layer thickness dependence of the effective mass in InAs/GaSb superlattices studied by high field cyclotron resonance

The effective mass has been studied in a series of semiconducting and semimetallic InAs/GaSb superlattices as a function of superlattice period and band gap. The mass is found to be determined almost entirely by the superlattice period, and is relatively insensitive to both the ratio of the InAs to GaSb thickness, and the structure of the interface layer, which was grown as both a monolayer of InSb and GaAs. Using pulsed magnetic fields of up to 180 T it was possible to observe spin-split cyclotron resonance at room temperature for all samples studied. On cooling the spin-splitting was found to be temperature dependent. This is attributed to the importance of electron-electron interactions which couple the two spin transitions as observed recently in high purity GaAs/GaAlAs heterojunctions at low temperatures.     

PCB线宽最大最小值的检测算法

随着线路板行业的发展,国内外客户对线路板产品的要求越来越高,线宽的检测不再仅限于对线宽平均值的检测,还需要检测出线宽的最大值和最小值,文章对线宽最值算设计进行简介,并通过实验对算法可行性进行验证,验证结果显示该最值算法具有逻辑可行性,且精度在一个像素3微米范围内,具有很强的实用性,为PCB检测行业增添一新的检测技术保障。     

PCB线宽检测设备的发展现状与趋势

印制电路板(PCB)在向高密度化和高性能化方向发展,导线精细化已成PCB生产的必然要求。在导体精细化过程中控制上线宽度和下线宽度以保证导线的电特性要求,已成各PCB生产厂家急需解决的关键问题。本文通过对目前常用PCB线宽检测设备的优缺点进行分析,提出了采用数字图像处理技术与照明技术的新一代的线宽/间距检测仪器设备,将成为印制板厂线宽检测的必备测量工具。     

Analysis of instability line width and white wall created by the photolithography process

In the photolithography processing of semiconductor, line width is smaller and smaller. Therefore, the requirements of process window are stricter than before. In the small line width, the formation of serious white wall will affect line width and cause rejects in following process. The study conducted research on the control of best focus in which particularly explored the relationship between exposure dose and line width and the phenomenon of white wall generated by focus. The research obtained related coefficients of exposure dose-line width and exposure dose-white wall by coating photo resist of different components with the same thickness on the surface of fused silica wafer. The results of research found that exposure dose might not only change line width but also had important effects on white wall. Among others, the most important factor for exposure dose is the component of sensitivity of photo resist.     

The influence of the passivation material on stress voiding in Al–Cu alloys

Storage tests have been performed to obtain information on the influence of the passivation material and its geometry on the mechanical reliability of Al–Cu lines. During storage tests, the stress in the lines is tensile and depends on the passivation material and passivation geometry. The passivation was either a SiO₂ layer or a SiN_x layer. In both cases the influence of a conformal and a planarised passivation geometry has been studied. Passivating the lines with a material with a higher stiffness such as SiN_x will increase the stress void density in the lines. Moreover, a conformal passivation layer induces less stress voids in the metal than a planarised passivation, deposited by a Dep/Etch method. The number of stress voids saturates within 24 h at 200°C. However, the voids continue to grow during longer storage times. When the lines are passivated with the lower stiffness material SiO₂, stress voids have not been observed after storage testing.     

The dependence of solar cell active layer resistance on illumination

In this study, an analysis of the sunlight concentration dependence of the active layer resistance in solar cells is presented. The analysis is essentially based on well-known classical models and has been worked out for the particular case of n⁺/p solar cells. This study leads to a relation between the excess carrier density and series resistance change. Interpretations based on our-results explain the experimental observations of Wolf and Rauschenbach (1963) and the theoretical investigation of Bobbio et al, (1977).     

The effects of electron irradiation and thermal dependence measurements on 4H-SiC Schottky diode

Semiconductors - In this paper the effects of high energy (3.0 MeV) electrons irradiation over a dose ranges from 6 to 15 MGy at elevated temperatures 298 to 448 K on the current-voltage...     

Capacitance measurements for diodes in the case of strong dependence of the diode-base series resistance on the applied voltage

Epitaxial-diffused 6H-SiC diodes incorporating a high-resistivity interlayer in the base were studied; the resistance of this interlayer varied when the forward-bias voltage was applied. It is shown that, in spite of the absence of direct indications of the effects of the series resistance (the capacitance is independent of frequency and the value of capacitive cutoff voltage is small), the capacitance measurements for such structures may be incorrect.     

基于FPGA的高分辨率红外触摸屏的设计

红外触摸的主要缺点是分辨率低下和易受到光干扰,从而不能实现准确定位。为了提高红外触摸屏的分辨率,准确确定触摸点的位置,通过对红外发光管和红外接收管在触摸时的特性进行分析,得知在触摸时,触摸会对某个邻域内的多个红外接收管造成影响,同时其影响因子存在差异。通过对红外接收管的模拟信号进行A/D转换,使其成为数字信号。再用所得的数字信号来构造影响因子,通过信号处理理论和模糊控制理论来构造线性函数的方法来实现触摸位置的确定。此外,还介绍了该红外触摸屏的硬件组成及其设计。通过对硬件平台的实验证明,在无强光干扰下,该红外触摸屏能够达到的分辨率为0.5 mm。     

机载高分辨率加固LCD显示器的设计

为了实现机载显示器高分辨率、大屏幕显示的目的,选用商用货架产品（COTS）,采用切割、拼接技术以及加固技术,对液晶屏进行了深入研究和设计。结果表明,在不损失分辨率和显示效果的情况下,该方法拼接屏显示器的拼接物理缝小于1.5 mm,分辨率达到3200×1200,完全实现了大屏幕超宽双屏显示的目的。该方法具有实用、成本低以及通用化的特点,完全能够满足低成本军用机载高分辨率LCD显示器的使用要求。