Modeling the Behavior of a MOS Transistor under Fast Neutron and Gamma Irradiation

A numerical model of trapping of the radiation-induced charge in the bulk and on the surface of the oxide layer of a MOS transistor has been developed. The model takes into account the generation of point defects under fast neutron irradiation. The volume and surface charges obtained by the numerical modeling have been used to calculate the drain—gate characteristic of the MOS transistor exposed to neutron irradiation in different doses and accompanying high-energy gamma-ray irradiation. To model the effect of neutron irradiation, different methods for estimating the rate of point defect generation in a two-component material (SiO2) have been developed. The simulated drain—gate characteristic is shown to agree well with the experimental data obtained at the concentration of hole traps and their capture cross sections lying within the published data for an unirradiated device after exposure to gamma rays from a 60Co gamma source and after irradiation with fast neutrons with an average energy of ∼1 MeV and accompanying gamma rays using a pool-type reactor.     

Effect of Temperature Variation on the Characteristics of Microwave Power AlGaN/GaN MODFET

The prime motivation for developing the proposed model of AlGaN/GaN microwave power device is to demonstrate its inherent ability to operate at much higher temperature. An investigation of temperature model of a 1 μm gate AlGaN/GaN enhancement mode n-type modulation-doped field effect transistor (MODFET) is presented. An analytical temperature model based on modified charge control equations is developed. The proposed model handles higher voltages and show stable operation at higher temperatures. The investigated temperature range is from 100 °K–600 °K. The critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak dc trans-conductance (g_m), and unity current gain cut-off frequency (f_T). The calculated values of f_T (10–70 GHz) at elevated temperature suggest that the operation of the proposed device has sufficiently high current handling capacity. The temperature effect on saturation current, cutoff frequency, and trans-conductance behavior predict the device behavior at elevated temperatures. The analysis and simulation results on the transport characteristics of the MODFET structure is compared with the previously measured experimental data at room temperature. The calculated critical parameters suggest that the proposed device could survive in extreme environments.     

Antireflection fianite and ZrO<Subscript>2</Subscript> coatings for solar cells

Fianite is a promising multipurpose material for new electronic technologies owing to its unique combination of physical and chemical properties. It can be used in virtually all of the main technological stages of the production of micro-, opto-, and SHF-electronics; in particular, as a bulk dielectric substrate and a material for buffer layers in heteroepitaxy; as a material for insulating, antireflection, and protective layers in device elements; and as a gate dielectric [1–3]. In this work, we consider the possibilities for using fianite and ZrO₂ as an antireflection coating for silicon solar cells (SCs) and SCs based on InGaAsP heterostructures.     

Quantitative analysis of charge-carrier trapping in organic thin-film transistors from transfer characteristics

A dynamic method for quantifying the amount and mechanism of trapping in organic field effect transistors (OFETs) is proposed. It exploits transfer characteristics acquired upon application of a triangular waveform gate sweep V _G. The analysis of the transfer characteristics at the turning point V _G=−V _max between forward and backward gate sweeps, viz. around the maximum gate voltage V _max applied, provides a differential slope Δm which depends exclusively on trapping. Upon a systematic change of V _max it is possible to extract the initial threshold voltage, equivalent to one of the observables of conventional stress measurements, and assess the mechanism of trapping via the functional dependence on the current. The analysis of the differential logarithmic derivative at the turning point yields the parameters of trapping, as the exponent β and the time scale of trapping τ. In the case of an ultra-thin pentacene OFET we extract β=1 and τ=10²–10³ s, in agreement with an exponential distribution of traps. The analysis of the hysteresis parameter Δm is completely general and explores time scales much shorter than those involved in bias stress measurements, thus avoiding irreversible damage to the device.     

Design and simulation of charge transport in single-electron transistor using TCAD numerical simulator

The ability to control the electron flow of a MOSFET is decreased due to the quantum mechanical effect when scaled down below 50 nm. Hence, A new field of device research is needed to complete this challenge. A device based on Tunneling phenomena is called a single-electron device. In this paper, the most fundamental single-electron device is a single-electron transistor (SET) designed using visual TCAD with a gate length and width of 2 nm. The channel is ultra-thin with a length of 2 nm and a width of 0.005 nm, and the channel thickness is 0.3 nm. Then a Si quantum dot of size 0.5 × 1.nm² is used between the island and the gate. Both the Devices are simulated using the Genius Simulator. And it is found that at room temperature, the device with Si dot is more efficient. The device with Si dot has less capacitance and higher charging efficiency than the device without the Quantum dot.     

Tin – an unlikely ally for silicon field effect transistors?

We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high‐κ/metal gate based multi‐gate‐field‐effect‐transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Three-qubit quantum-gate operation with an SQUID in a cavity

We propose a method of realizing a three-qubit quantum gate with a superconducting quantum interference device(SQUID) in a cavity.In this proposal,the gate operation involves the SQUID ground-states and the Fock states of cavity modes b and c.The two field-modes act as the controlling qubits,and the two SQUID states form the target qubit.Since only the metastable lower levels are involved in the gate operation,the gate is not affected by the SQUID decay rates.     

新型槽栅nMOSFET凹槽拐角效应的模拟研究

应用二维器件仿真程序PISCES Ⅱ，模拟计算了新型槽栅结构器件中凹槽拐角效应的影响与作用，讨论了槽栅结构MOSFET的沟道电场特征及其对热载流子效应、阈值电压特性等的影响.槽栅结构的凹槽拐角效应对抑制短沟道效应和抗热载流子效应是十分有利的，并且拐角结构在45°左右时拐角效应最大.调节拐角与其他结构参数，器件的热载流子效应、阈值电压特性、亚阈值特性、输出特性等都会有较大的变化. 关键词： 槽栅MOSFET 拐角效应 阈值电压 热载流子退化     

Nanocrystalline ruthenium oxide and ruthenium in sensing applications – an experimental and theoretical study

In this project, we have explored RuO₂ and Ru nanoparticles (∼ ∼10 and ∼ ∼5 nm, respectively, estimated from XRD data) to be used as gate material in field effect sensor devices. The particles were synthesized by wet chemical procedure. The capacitance versus voltage characteristics of the studied capacitance shifts to a lower voltage while exposed to reducing gases. The main objectives are to improve the selectivity of the FET sensors by tailoring the dimension and surface chemistry of the nanoparticles and to improve the high temperature stability. The sensors were characterized using capacitance versus voltage measurements, at different frequencies, 500 Hz to 1 MHz, and temperatures at 100–400°C. The sensor response patterns have been found to depend on operating temperature. X-ray photoelectron spectroscopy (XPS) analyses were performed to investigate the oxidation state due to gas exposure. Quantum-chemical computations suggest that heterolytic dissociative adsorption is favored and preliminary computations regarding water formation from adsorbed hydrogen and oxygen was also performed.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

Lifetimes of electrons in the Shockley surface state band of Ag(111)

We present a theoretical many-body analysis of the electron–electron (e–e) inelastic damping rate Γ of electron-like excitations in the Shockley surface state band of Ag(111). It takes into account ab initio band structures for both bulk and surface states. Γ is found to increase more rapidly as a function of surface state energy E than previously reported, thus leading to an improved agreement with experimental data. PACS 73.20.At; 68.37.Ef; 72.15.Lh     

Metal-oxide-semiconductor field effect transistor using ‘oxidizedμc-Si/ultrathin oxide’ gate structure

The metal-oxide-semiconductor (MOS) field effect transistor (FET) using ‘oxidized μ c-Si/ultrathin oxide’ gate structure was studied. It was found that this structure shows negative differential resistance behavior, which can be explained by the Coulomb blockade effect of trapped carriers and immediate tunneling into and tunneling out with gate bias variation. The requirements for the device with this structure showing negative differential resistance behavior are based on very weak resistive coupling between floating gate and channel. They are the thinness of the tunnel oxide film, the thickness ratio of the upper oxidized film and the tunnel oxide, and the channel threshold voltage. MOSFET with this gate structure is proposed as a new negative differential resistance device.     

离子凝胶薄膜栅介石墨烯场效应管

在石墨烯场效应晶体管栅介结构中引入具有良好电容特性或极化特性的材料可改善晶体管性能.本文采用化学气相沉积制备的石墨烯并以PVDF-[EMIM]TF2N离子凝胶薄膜(ion-gel film)作为介质层制备底栅型石墨烯场效应管(graphene-based field effect transistor, GFET),研究其电学特性以及真空环境和温度对GFET性能的影响.结果表明离子凝胶薄膜栅介石墨烯场效应晶体管表现出良好的电学特性,室温空气环境中,与SiO_2栅介GFET相比, ion-gel膜栅介GFET开关比(J_(on)/J_(off))和跨导(g_m)分别提高至6.95和3.68×10~(–2) mS,而狄拉克电压(V_(Dirac))低至1.3 V;真空环境下ion-gel膜栅介GFET狄拉克电压最低可降至0.4 V;随着温度的升高, GFET的跨导最高可提升至6.11×10~(–2) mS.     

一种基于双栅材料的单极性类金属氧化物半导体碳纳米管场效应管设计方法

由于导电沟道-源/漏电极界面处可能发生的载流子带间隧穿,传统类金属氧化物半导体(MOS)碳纳米管场效应管呈现双极性传输特性,极大影响了器件性能的提高及其在电路中的应用.为获得具有理想单极性传输特性的类MOS碳纳米管场效应管,本文提出了一种基于双栅材料的器件设计方法.模拟结果表明,通过合理选取调节电极材料,在不影响器件亚阈值斜率的同时,该设计方法不仅能使开关电流比增大6—9个数量级,有效调节阈值范围,而且能有效消除传统类MOS碳纳米管场效应管的双极性传输特性.进一步研究表明,该设计所获得的器件性能提高与调节     

Off-state breakdown characteristics of InGaP-based high-barrier gate heterostructure field-effect transistors

In this work, the off-state breakdown characteristics of two different types InGaP-based high-barrier gate heterostructure field-effect transistors are studied and demonstrated. These devices have different high-barrier gate structures, e.g. the i-InGaP layer for device A and n  ⁺ - GaAs/p ⁺  -InGaP/n-GaAs camel-like structure for device B. The wide-gap InGaP layer is used to improve the breakdown characteristics. Experimentally, the studied devices show high off-state breakdown characteristics even at high temperature operation regime. This indicates that the studied devices are suitable for high-power and high-temperature applications. In addition, the off-state breakdown mechanisms are different for device A and B. For device A, off-state breakdown characteristics is only gate dominated at the temperature regime from 30 to 180  ^∘ C. For device B, off-state breakdown characteristics are gate and channel dominated at 30  ^∘ C and only gate dominated within 150 to 210  ^∘ C.     

Impacts of Ti on electrical properties of Ge metal–oxide–semiconductor capacitors with ultrathin high-k LaTiON gate dielectric

Ge Metal–Oxide–Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La₂O₃ ratio, a suitable Ti/La₂O₃ ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×10¹¹ eV⁻¹ cm⁻², and relatively low gate-leakage current density of 2.0×10⁻³ A cm⁻² at a gate voltage of 1 V.     

Modeling interface trapping effect in organic field-effect transistor under illumination

Organic field-effect transistors (OFETs) have received significant attention recently because of the potential application in low-cost flexible electronics. The physics behind their operation are relatively complex and require careful consideration particularly with respect to the effect of charge trapping at the insulator–semiconductor interface and field effect in a region with a thickness of a few molecular layers. Recent studies have shown that the so-called “onset” voltage (V _onset) in the rubrene OFET can vary significantly depending on past illumination and bias history. It is therefore important to define the role of the interface trap states in more concrete terms and show how they may affect device performance. In this work, we propose an equivalent-circuit model for the OFET to include mechanism(s) linked to trapping. This includes the existence of a light-sensitive “resistor” controlling charge flow into/out of the interface trap states. Based on the proposed equivalent-circuit model, an analytical expression of V _onset is derived showing how it can depend on gate bias and illumination. Using data from the literature, we analyzed the I–V characteristics of a rubrene OFET after pulsed illumination and a tetracene OFET during steady-state illumination.     

Mismatch of dielectric constants at the interface of nanometer metal-oxide-semiconductor devices with high-<Emphasis Type="Italic">K</Emphasis> gate dielectric impacts on the inversion charge density

The comparison of the inversion electron density between a nanometer metal-oxide-semiconductor (MOS) device with high-K gate dielectric and a SiO₂ MOS device with the same equivalent oxide thickness has been discussed. A fully self-consistent solution of the coupled Schr?dinger–Poisson equations demonstrates that a larger dielectric-constant mismatch between the gate dielectric and silicon substrate can reduce electron density in the channel of a MOS device under inversion bias. Such a reduction in inversion electron density of the channel will increase with increase in gate voltage. A reduction in the charge density implies a reduction in the inversion electron density in the channel of a MOS device. It also implies that a larger dielectric constant of the gate dielectric might result in a reduction in the source–drain current and the gate leakage current.     

High on/off current ratio in ballistic CNTFETs based on tuning the gate insulator parameters for different ambient temperatures

A theoretical study is presented on the on/off current ratio limits for a ballistic coaxially-gated carbon nanotube field effect transistor (CNTFET) with highly doped source/drain regions. Based on changes in gate insulator dielectric constant and thickness, the current ratio has been estimated at different ambient temperatures. Decreasing the gate insulator thickness after a certain value around 3 nm causes the current ratio to degrade drastically. Although the higher dielectric constant values have a fair effect on current ratio, this effect could be suppressed when the device with a low gate insulator thickness works at a low ambient temperature. The simulation results also show that the temperature drastically degrades the current ratio value; whereas in a certain range of ambient temperature, tuning the values of gate insulator thickness and dielectric constant could be very helpful. In this way, the optimum values of gate insulator thickness and dielectric constant are identified to offer the highest on/off current ratio of the device.     

Investigation of InGaP/InGaAs n- and p-channel pseudomorphic modulation-doped field effect transistors with high gate turn-on voltages

The performances of InGaP/InGaAs camel-gate n- and p-channel pseudomorphic modulation-doped field effect transistors (MODFETs) are demonstrated and compared. In the n-channel (p-channel) device, an extremely high gate turn-on voltage of 1.7 (2.0) V is measured due to the pn depletion in the camel-like gate region and the presence of a large conduction (valence) band discontinuity at the InGaP/InGaAs heterostructure. In addition, a maximum drain saturation current of 425 mA/mm (−345 mA/mm) and a maximum transconductance of 85 mS/mm (63 mS/mm) are obtained for the n-channel (p-channel) device. These excellent characteristics indicate that the devices that are studied are promising for signal amplifiers and inverter circuit applications.