Thermal annealing effects on a compositionally graded SiGe layer fabricated by oxidizing a strained SiGe layer

Thermal annealing effects on a thin compositionally graded SiGe buffer layer on silicon substrate fabricated by oxidizing a strained SiGe layer are investigated with X-ray diffraction, ultraviolet Raman spectra and atomic force microscopy. Interestingly, we found that the surface roughness and the threading dislocation densities are kept low during the whole annealing processes, while the Ge concentration at the oxidizing interface decreases exponentially with annealing time and the strain in the layer is only relaxed about 66% even at 1000 °C for 180 min. We realized that the strain relaxation of such a compositionally graded SiGe buffer layer is dominated by Si-Ge intermixing, rather than generation and propagation of misfit dislocations or surface undulation.     

Epitaxial growth of fully relaxed Si0.75Ge0.25 on SOI substrate

A fully relaxed Si_0.75Ge_0.25 film with low dislocation densities is fabricated by epitaxial growth on SOI substrate without depositing graded buffers. The relaxation mechanism of the SiGe layer directly grown on SOI substrate is also analyzed. For SiGe grown on SOI with low Ge content, the strain is redistributed between SiGe and the top Si of SOI substrate, and the strain residing in SiGe layer can be fully relaxed by the formation and expansion of dislocation half-loops near the SiGe/Si interface. The surface morphology and crystal quality of all samples are analyzed by optical microscopy and transmission electron microscopy (TEM), respectively. Compared to the Si_0.75Ge_0.25 layer epitaxially grown on graded buffer, the Si_0.75Ge_0.25 directly grown on SOI substrate appears good surface morphology and perfect crystal quality.     

Formation of relaxed SiGe on the buffer consists of modified SiGe stacked layers by Si pre-intermixing

High-quality relaxed SiGe films on Si (0 0 1) have been demonstrated with a buffer layer containing modified SiGe (m-SiGe) islands in ultra-high vacuum chemical vapor deposition (UHV/CVD) system. The m-SiGe islands are smoothened by capping an appropriate amount of Si and the subsequent annealing for 10 min. This process leads to the formation of a smooth buffer layer with non-uniform Ge content. With the m-SiGe-dot multilayer as a buffer layer, the 500-nm-thick uniform Si_0.8Ge_0.2 layers were then grown. These m-SiGe islands can serve as effective nucleation centers for misfit dislocations to relax the SiGe overlayer. Surface roughness, strain relaxation, and crystalline quality of the relaxed SiGe overlayer were found to be a function of period's number of the m-SiGe-dot multilayer. By optimizing period number in the buffer, the relaxed Si_0.8Ge_0.2 film on the 10-period m-SiGe-dot multilayer was demonstrated to have a threading dislocation density of 2.0 × 10⁵ cm⁻² and a strain relaxation of 89%.     

Strain relaxation in SiGe layer during wet oxidation process

The strain relaxation in SiGe layer on silicon substrate during wet oxidation at 1000 °C was investigated. It was proposed that the competition between Ge accumulation and diffusion led to different strain-relaxation behaviors. At the very beginning, Ge atoms at the oxidizing interface were quickly accumulated due to the high oxidation rate resulting in the additional nucleation of misfit dislocations (therefore a lot of threading dislocations) to relieve stress after the thickness of the Ge condensed layer was larger than the critical value. And then, when the Ge accumulation rate was less than the diffusion rate, Ge content started to decrease from a maximum value and the strain in the SiGe layer was mainly relieved through surface roughing and the degree of strain relaxation reached a maximum. When the samples were further oxidized, Ge accumulation could be neglected because of the self-limiting oxidation and the Ge diffusion dominated the consequent processes. As a result, Ge content at the interface was reduced, with the contribution of the strain relaxation in SiO₂ viscously, leading to the decrease of degree of strain relaxation in the SiGe layers slowly.     

应变Si沟道nMOSFET阈值电压模型

在研究分析弛豫SiGe衬底上的应变Si 沟道nMOSFET纵向电势分布的基础上,建立了应变Si nMOSFET阈值电压模型,并利用该模型对不同的器件结构参数进行仿真,获得了阈值电压与SiGe层掺杂浓度和Ge组分的关系、阈值电压偏移量与SiGe层中Ge组分的关系、阈值电压与应变Si层掺杂浓度和厚度的关系. 分析结果表明：阈值电压随SiGe层中Ge组分的提高而降低,随着SiGe层的掺杂浓度的提高而增大;阈值电压随应变Si层的掺杂浓度的提高而增大,随应变Si层厚度增大而增大. 该模型为应变Si 器件阈值电压设计 关键词： 应变硅 阈值电压 电势分布 反型层     

Evolution of Ge and SiGe Quantum Dots under Excimer Laser Annealing

We present different relaxation mechanisms of Ge and SiGe quantum dots under excimer laser annealing. Investigation of the coarsening and relaxation of the dots shows that the strain in Ge dots on Ge films is relaxed by dislocation since there is no interface between the Ge dots and the Ge layer, while the SiGe dots on Si0.77Ge0.23 film relax by lattice distortion to coherent dots, which results from the obvious interface between the SiGe dots and the Si0.77Ge0.23 film. The results are suggested and sustained by Vanderbilt and Wickham＇s theory, and also demonstrate that no bulk diffusion occurs during the excimer laser annealing.     

基于低温硅技术的赝晶SiGe应变弛豫机理

基于能量平衡条件,结合低温硅(LT-Si)剪切模量小于SiGe的实验结果,从螺位错形成模型出发,给出了基于LT-Si技术的赝晶SiGe应变弛豫机理.该机理指出,赝晶SiGe薄膜厚度小于位错形成临界厚度,可通过LT-Si缓冲层中形成位错释放应变;等于与大于临界厚度,位错在LT-Si层中优先形成,和文献报道中已观察到的实验结果相符合.同时,实验制备了基于LT-Si技术的弛豫Si_0.8Ge_0.2虚拟衬底材料.结果显示,位错被限制在LT-Si缓冲层中,弛豫度达到了85.09%,且在Si_0.8Ge_0.2中未观察到穿透位错,实验结果证实了赝晶Si_0.8Ge_0.2是通过在LT-Si缓冲层形成位错来释放应变的弛豫机理. 关键词： 低温硅 赝晶锗硅 弛豫机理 位错理论     

Growth of High Quality Strained-Si on Ultra-Thin SiGe-on-Insulator Substrate

Ultra-thin and near-fully relaxed SiCe substrate is fabricated using a modified Ce condensation technique, and then a 25-nm-thiek biaxially tensile strained-Si with a low rms roughness is epitaxially deposited on a SiGe- on-Insulator （SGOI） substrate by ultra high vacuum chemical vapor deposition （UHVCVD）. High-Resolution cross-sectional transmission electron microscope （HR-XTEM） observations reveal that the strained-Si/SiGe layer is dislocation-free and the atoms at the interface are well aligned. Furthermore, secondary ion mass spectrometry （SIMS） results show a sharp interface between layers and a uniform distribution of Ge in the SiCe layer. One percent in-plane tensile strain in the strained-Si layer is confirmed by ultraviolet （UV） Raman spectra, and the stress maintained even after a 30-s rapid thermal annealing （RTA） process at 1000℃. According to those results, devices based on strained-Si are expected to have a better performance than the conventional ones.     

Relaxed SiGe-on-insulator with high Ge fraction obtained by oxidation of SiGe/Si-on-insulator with hydrogen ions implantation

The SiGe-on-insulator (SGOI) materials were obtained by thermal oxidation of SiGe layers on SOI wafers. As a comparison, H ions were implanted into SiGe layer of some samples before oxidation. The high degree relaxed SGOI materials with high Ge fraction were fabricated by two kinds of samples, including the samples without and with H ions implantation, and relaxation degree of SiGe layers is above 93%. The different result is that implantation of H ions decreased the oxidation rate of SiGe layer and decreased the loss of Ge in SiGe layer during oxidation. The effect of implantation of H ions is discussed in the paper.     

Thermal stability of SiGe films on an ultra thin Ge buffer layer on Si grown at low temperature

The thermal stability of SiGe films on an ultra thin Ge buffer layer on Si fabricated at low temperature has been studied. The microstructure and morphology of the samples were investigated by high-resolution X-ray diffraction, Raman spectra and atomic force microscopy, and using a diluted Secco etchant to reveal dislocation content. After thermal annealing processing, it is observed that undulated surface, threading dislocations (TDs) and stacking faults (SFs) appeared at the strained SiGe layer, which developed from the propagation of a misfit dislocation (MD) during thermal annealing, and no SFs but only TDs formed in strain-relaxed sample. And it is found that the SiGe films on the Ge layer grown at 300 °C has crosshatch-free surface and is more stable than others, with a root mean square surface roughness of less than 2 nm and the threading dislocation densities as low as ∼10⁵ cm⁻². The results show that the thermal stability of the SiGe films is associated with the Ge buffer layer, the relaxation extent and morphology of the SiGe layer.     

Strain relaxation in nano-patterned strained-Si/SiGe heterostructure on insulator

In order to evaluate the strain stability, arrays of strained Si/SiGe nano-stripes and nano-pillars were fabricated by Electron-Beam Lithography (EBL) and Reactive-Ion Etching (RIE). The strain relaxation in the patterned strained Si on SiGe-on-insulator (SGOI) was investigated by high-resolution UV micro-Raman spectroscopy. The Raman measurements before and after patterning indicate that most of the strain in the top strained Si is maintained until scaling down to 300 nm, and relaxation of <15% is observed in pillars with a dimension of 150 nm × 150 nm. In the nano-patterned heterostructure strained Si/SiGe, the observed relaxation is small, which is mainly attributed to the fully relaxed and dislocation-free SiGe virtual substrate fabricated by modified Ge condensation.     

X-ray triple-axis diffractometry investigation of Si/SiGe/Si on silicon-on-insulator subjected to in situ low-temperature annealing

X-ray triple-axis diffractometry (XRTD) was used to characterize heterostructure Si/SiGe/Si on silicon-on-insulator (SOI) subjected to in situ low-temperature annealing. Crystallographic tilt, lattice constant and relaxation percentage were examined, respectively. Two peaks have been observed in (0 0 4) reciprocal lattice mappings (RLMs) of Si layers. The (0 0 4) RLMs indicate that Si cladding is in tensile strain. We have also found two peaks with different k_∥ and k_⊥ in (1 1 3) asymmetric RLMs of Si layers. It is deduced from comprehensive analyses on (0 0 4) and (1 1 3) RLMs that Ge diffusion and in-plane tensile strain lead to 2θ shift of the Si layers underneath SiGe layer in (0 0 4) RLMs. And the diffusion concentration of Ge accurately determined by XRTD is mole fraction 0.84%.     

Strain relaxation of epitaxial SiGe layer and Ge diffusion during Ni silicidation on cap-Si/SiGe/Si(0 0 1)

Strain relaxation of the epitaxial SiGe layer and Ge diffusion during nickel silicidation by rapid thermal annealing the structure of Ni(≅14 nm)/cap-Si(≅26 nm)/Si_0.83Ge_0.17/Si(0 0 1) at the elevated annealing temperatures, T_A, were investigated by X-ray diffraction analyses of high-resolution ω-2θ scan and reciprocal space mapping. The analyses showed a much larger strain relaxation at a lower T_A and a reduction in Ge content in the SiGe layer of Ni/SiGe/Si(0 0 1) after thermal annealing compared to the case of cap-Si/SiGe/Si(0 0 1). The results indicate that the strain relaxation of the SiGe layers in NiSi/SiGe/Si(0 0 1) is related to the phenomena of NiSi agglomeration and penetration into the SiGe layer during silicidation at elevated anneal temperatures ≥750 °C. At elevated T_A ≥ 750 °C, Ge diffused into the intact cap-Si area during silicidation.     

Effect of strain relaxation of oxidation-treated SiGe epitaxial thin films and its nanomechanical characteristics

In this study, we examined the effect of high-temperature oxidation treatment on the SiGe epitaxial thin films deposited on Si substrates. The X-ray diffraction (XRD), atomic force microscopy (AFM), and nanoindentation techniques were employed to investigate the crystallographic structure, surface roughness, and hardness (H) of the SiGe thin films, respectively. The high-temperature oxidation treatment led to Ge pileup at the surface of the SiGe thin films. In addition, strain relaxation occurred through the propagation of misfit dislocations and could be observed through the cross-hatch pattern (800-900 °C) and SiGe islands (1000 °C) at the surface of the SiGe thin films. Subsequent hardness (H) measurement on the SiGe thin films by continuous penetration depth method indicated that the phenomenon of Ge pileup caused a slightly reduced H (below 50 nm penetration depth), while relaxation-induced defects caused an enhanced H (above 50 nm penetration depth). This reveals the influence of composition and defects on the structure strength of high-temperature oxidation-treated SiGe thin films.     

Highly-ordered SiGe-islands grown by dislocation patterning using ion-assisted MBE

Fabrication of device structures based on laterally self-ordered systems without the use of expensive and time-consuming nanolithography could have undoubted advantages. For such applications, it is proposed to use misfit dislocation networks from partially relaxed SiGe layers on (1 0 0) Si substrate as a template for the growth of highly ordered SiGe islands. Ion bombardment during molecular beam epitaxy of metastable SiGe layers leads to such a partial relaxation by misfit dislocation networks. The ions are generated by the interaction of the evaporated Si flux with the electrons in an electron beam evaporator, which causes a partial ionization of Si atoms in the molecular beam. We demonstrate by atomic force microscopy that subsequent growth of SiGe on such relaxed SiGe (25-50% Ge) layers leads to the formation of uniform three-dimensional islands highly ordered in 〈1 1 0〉 directions.     

Oxidation process of SiGe on SOI substrates

The oxidation of SiGe film epitaxial grown on top of SOI wafers has been studied. These SiGe/SOI samples were oxidized at 700, 900, 1100 °C. Germanium atoms were rejected from SiGe film to SOI layer. A new Si_1−xGe_x (x is minimal) layer formed at SiGe/Si interface. As the germanium atoms diffused, the new Si_1−xGe_x (x is minimal) layer moved to Si/SiO₂ interface. Propagation of threading dislocation in SiGe film to SOI substrate was hindered by the new SiGe/Si interface. Strain in SOI substrate transferred from SiGe film was released through dislocation nucleation and propagation inner. The relaxation of SiGe film could be described as: strain relaxed through strain equalization and transfer process between SiGe film and SOI substrates. Raman spectroscopy was used to characterize the strain of SiGe film. Microstructure of SiGe/SOI was observed by transmission electron microscope (TEM).     

Evolution of stress and strain relaxation of Ge and SiGe alloy films on Si(0 0 1)

The growth of Ge and SiGe alloy films on Si substrates has attracted considerable interest in the last years because of their importance for optoelectronic devices as well as Si-based high speed transistors. Here we give a short overview on our recent real time stress measurements of Ge and SiGe alloy films on Si(0 0 1) performed with a sensitive cantilever beam technique and accompanied by structural investigations with atomic force microscopy. Characteristic features in the stress curves provide detailed insight into the development and relief of the misfit strain. For the Stranski–Krastanow system Ge/Si(0 0 1) as well as for SiGe films with Si contents below 20%, the strain relaxation proceeds mainly into two steps: (i) by the formation of 3D islands on top of the Ge wetting layer; (ii) via misfit dislocations in larger 3D islands and upon their percolation.     

Fabrication of high Ge content SiGe-on-insulator with low dislocation density by modified Ge condensation

A SiGe-on-insulator (SGOI) structure with high Ge content and low density of dislocations is fabricated by a modified Ge condensation technique. The formation and elimination of stacking faults during condensation process are analyzed by transmission electron microscopy. A Si_0.19Ge_0.81OI substrate is fabricated utilizing two steps of oxidation and intermittent annealing. The time of oxidation or annealing at 900 °C is essential for the elimination of stacking faults in high Ge content SGOI substrate. The surface morphology of SGOI is investigated by atomic force microscopy and the defect density is evaluated from wet etching method. After the final condensation, the surface root-mean-square roughness (rms) of SiGe layer is kept below 1 nm and the threading defect density is controlled around 10⁴ cm⁻². The smooth surface and integrated lattice structure of SiGe layer indicate that the SGOI is suitable for heteroepitaxial growth of strained Ge, GaAs and III-V compounds.     

Characteristics of surface and waveguide emitting SiGe : Er : O diodes

In this paper we demonstrate electroluminescence from erbium- and oxygen doped Si and SiGe diodes in surface emitting and waveguiding geometry. The layers were deposited by molecular beam epitaxy (MBE) on (1 0 0)Si. A series of samples with varying Er : O-doped layer thickness was grown, showing a decrease in luminescence intensity for layers thinner than 80 nm. The current–voltage characteristics and luminescence properties of another series of samples with varying Ge content were examined. They are probably influenced by strain relaxation at large Ge content. Si/SiGe waveguides were processed and their emission was analyzed by a confocal microscope setup. The spatially narrow emission and the dependence of luminescence on waveguide length proved optical guiding of the erbium emission.     

Non-homogeneous SiGe-on-insulator formed by germanium condensation process

Ge condensation process of a sandwiched structure of Si/SiGe/Si on silicon-on-insulator （SOI） to form SiGe-on- insulator （SGOI） substrate is investigated. The non-homogeneity of SiGe on insulator is observed after a long time oxidation and annealing due to an increased consumption of silicon at the inflection points of the corrugated SiGe film morphology, which happens in the case of the rough surface morphology, with lateral Si atoms diffusing to the inflection points of the corrugated SiGe film. The transmission electron microscopy measurements show that the non-homogeneous SiGe layer exhibits a single crystalline nature with perfect atom lattice. Possible formation mechanism of the non-homogeneity SiGe layer is presented by discussing the highly nonuniform oxidation rate that is spatially dependent in the Ge condensation process. The results are of guiding significance for fabricating the SGOI by Ge condensation process.