适用于高速亚微米CMOS工艺的超薄SOI

本文评述了超薄SOI结构的性能优点,并对需要由SOI工业指明的工艺因素和市场驱动因素做了预测。     

用于亚微米CMOS的自对准硅化钛工艺

本文研究了用溅射钛和快速退火法与硅反应形成硅化钛的工艺,二氧化硅侧墙轻掺杂漏结构的CMOS工艺加上该工艺后,器件的阈值电压、源漏击穿电压没有明显变化,但使CMOS的栅电阻降低一个数量级,源漏串联电阻为原来的1/4。肌此工艺已研制成功3μm NMOS 12位乘法器,比没有硅化物的器件速度提高一倍。     

亚微米CMOS结构光学交叉互连电路芯片的设计

同单路光接收／发送电路系统相比,采用单片集成的多路交叉互连接收／发送系统可实现大容量信息交换和高度复杂的信息处理。给出了与１０×１０阵列多量子阱（ＭＱＷ）器件芯片倒扣连接的接收／发送交叉互连电路的设计,芯片电路采用０．３５／０．５μｍ设计规则、三层金属布线ＣＭＯＳ结构,在２ｍｍ×２ｍｍ芯片上,可完成１６路接收／发送及１６×１６信号交叉互连的功能。     

亚微米自对准硅化钛CMOS工艺

本文对两步快速热退火形成ＴｉＳｉ２的工艺及其工艺的兼容性、ＴｉＳｉ２的物理化学物性进行了研究，结合ＬＤＤ结构，形成了两步快速热退火亚微米自对准硅化钛ＣＭＯＳ工艺，并应用于集成电路的制造，改善了电路性能。     

亚微米CMOS阈值电压控制研究

由于亚微米器件的短沟道效应，引起器件的阈值电压下降。本文的研究表明，对器件的沟道采取多次杂注入掺杂技术，可有效地克服短沟道效应与热载流子效应，即使在沟道长度为０．５μｍ时，器件仍显示出良好的效果。     

采用多次离子注入调整亚微米CMOS电路的阈电压

采用多次离子注入来调整亚微米CMOS的NMOS和PMOS管的阈值电压是研究亚微米CMOS电路的关键.浅离子注入调节表面掺杂浓度以达到调整阈值电压的目的.深离子注入调整源漏穿通电压.与LDD、硅化物工艺相合,已研制出0.5μm的CMOS 27级环振电路,门延迟为130ps.     

薄膜亚微米CMOS／SOS工艺的开发及其器件的研制

本文较为详细地介绍了薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺技术的开发过程，薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺主要包括双固相外延，双层胶光刻形成亚微米细线条硅栅、Ｈ２－Ｏ２合成氧化薄栅氧化层以及快速退火等新的工艺技术，利用这套工艺成功地研制出了高性能薄膜来微米ＣＭＯＳ／ＳＯＳ器件和门延迟时间仅为１７７ｐｓ的１９级ＣＭＯＳ／ＳＯＳ环形振荡器，与厚膜器件相比，薄膜全耗尺器件和电路的性能得到了明显的提高。     

亚微米CMOS IC中自对准硅化物工艺的研究

自对准硅化钛工艺有许多重要的优点.但也存在栅氧化物的完整性、硅化物桥接短路、pn结损伤、二极管特性退化等问题.文章针对这些问题,在硅化前和硅化后的清洗、硅化的快速退火处理、接触电阻最佳化以及在硅化物上的接触孔腐蚀的选择性等方面进行了改进,有效地解决了问题.     

基于Taurus Workbench的亚微米n沟MOS器件关键工艺参数的优化

简要介绍了集成电路虚拟工厂系统Taurus Workbench。对亚微米n沟MOS工艺的特点进行了分析。在Taurus Workbench环境下进行亚微米n沟MOS器件关键工艺参数的优化，优化结果印证了新工艺条件对器件性能的改善。     

基于传统的CMOS工艺延伸漏极NMOS功率管研究

延伸漏极N型MOS（EDNMOS）是基于传统低成本CMOS工艺设计制造,用N-well作为NMOS漏极漂移区,以提高其击穿电压。用二维器件模拟软件Medicici对该器件进行模拟分析,结果表明有效地提高了NMOS管击穿电压。实验结果表明采用这种结构能使低压CMOS工艺输出功率管耐压提高到电源电压的2．5倍,样管在5V栅压下输出的电流可达到750mA。作为开关管工作,对于1000pF容性负载,其工作电流在550mA时,工作频率可达500KHz。     

采用新的抬高源漏工艺技术制作的全耗尽SOI CMOS器件和电路

采用新的工艺技术,成功研制了具有抬高源漏结构的薄膜全耗尽SOI CMOS器件.详细阐述了其中的关键工艺技术.器件具有接近理想的亚阈值特性,nMOSFETs和pMOSFETs的亚阈值斜率分别为65和69mV/dec.采用抬高源漏结构的1.2μm nMOSFETs的饱和电流提高了32%,pMOSFETs的饱和电流提高了24%.在3V工作电压下101级环形振荡器电路的单级门延迟为75ps.     

Elevated Source/Drain Engineering by Novel Technology for Fully Depleted SOI CMOS Devices and Circuits

0.35μm thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Analytical modelling for the current-voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs

An analytical drain current model for undoped (or lightly-doped) symmetric double-gate (DG) MOSFETs is presented. This model is based on the subthreshold leakage current in weak inversion due to diffusion of carriers from source to drain and an analytical expression for the drain current in strong inversion of long-channel DG MOSFETs, both including the short-channel effects. In the saturation region, the series resistance, the channel length modulation, the surface-roughness scattering and the saturation velocity effects were also considered. The proposed model has been validated by comparing the transfer and output characteristics with simulation and experimental results.     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

TiN栅及抬高源漏的薄膜全耗尽SOI CMOS器件的模拟研究

对0．25μm TiN栅及抬高源漏的薄膜全耗尽SOI CMOS器件进行了模拟研究。由于TiN栅具有中间禁带功函数，在低的工作电压下，NMOS和PMOS的阈值电压都得到了优化。随硅膜厚度的减小，釆用源漏抬高结构，减小了源漏串联电阻。采用抬高源漏结构的NMOS和PMOS，其饱和电流分别提高了36％和41％。由于采用源漏抬高能进一步降低硅膜厚度，短沟道效应也得到了抑制．     

亚0.1μm栅长CMOS器件和电路的研制

利用侧墙图形转移实现亚 0 .1μm栅线条 ,重掺杂多晶硅做固相扩散源实现 CMOS晶体管超浅源漏扩展区 ,并且将二者有机结合起来 ,成功实现了栅长约为 84 .6 nm的 CMOS器件和电路 .报道了利用重掺杂多晶硅固相扩散同时实现 CMOS源漏扩展区的方法 .