Advanced quantum dot and photonic crystal technologies for integrated nanophotonic circuits

Two types of nanophotonic technologies—two-dimensional photonic crystal (2D PC) slab waveguides (WGs) and quantum dots (QDs)—were developed for key photonic device structures in the future. For an ultrafast digital photonic network, an ultrasmall and ultrafast symmetrical Mach–Zehnder (SMZ)-type all-optical switch (PC-SMZ) and an optical flip–flop device (PC-FF) have been developed. To realize these devices, one method is to develop a selective-area molecular beam epitaxial growth QD technique by employing a metal mask method. Another method is to establish a new design method, i.e., topology optimization of the 2DPC WG with a wide and flat bandwidth, high transmittance, and low reflectivity. We also fabricated an optical microcavity in a photonic crystal slab embedded with GaAs QDs by droplet epitaxy. The Purcell effect on the exciton emission of GaAs QDs was confirmed by microphotoluminescence and lifetime measurements.     

P-I-N isolation for monolithic integrated circuits

A new isolation scheme is described in which the device is fabricated in an intrinsic region isolated from other regions and from theP^{+}substrate by aP-I-Nstructure. Thus the component-to-substrate capacitance and the substrate resistance are reduced by one order of magnitude or more, and the coupling or crosstalk is consequently reduced by several orders of magnitude. The fabrication process involves only conventional epitaxy and diffusion techniques. The intrinsic regions are obtained through gold compensation. Compared toP-N-junction-isolated gold-doped integrated devices, theP-I-N-isolated circuits require only one additional step-a second epitaxial deposition. Preliminary experimental data giveP-I-Ncapacitance of about 0.013 pF/mil²and breakdown voltage of 200 volts.     

Compact $$3\times 3$$ wavelength routing for photonic integrated circuits

Photonic integrated circuits are the future of optical communication networks. The demand for high bandwidth has added a remarkable increase in the capacity of transmission and routing techniques for optical networks. With massive growth in photonic integrated circuits, communication within them (PIC) is an area that needs to be explored and addressed. The signal path between different components in the circuit has to be established for an optimal path with high transmission efficiency. This could be achieved using routers. With this being the intention, this paper proceeds with a design of two \(3\,\times \,3\) optical passive wavelength routers using photonic crystal ring resonators. The designed router connects three transmitters to three receivers with desired characteristics such as low crosstalk, less propagation delay, low insertion loss and can be easily fabricated because of its less complex design. The routers are designed to operate in third transmission window wavelength with basic building blocks of \(1\,\times \,2\) routers. The designed layout of routers exhibits good performance which can be used for all optical communication networks and has a good technological compatibility for chip level integration in PIC. The layout is simulated using finite difference time domain and plane wave expansion methods.     

High sensitive photonic crystal ring resonator structure applicable for optical integrated circuits

Quality factor and refractive sensitivity are significant parameters in designing optical devices such as filters, demultiplexers, switches and sensors. In this paper, we proposed a novel structure for photonic crystal ring resonator with octagon-shaped core. The transmission efficiency of the proposed ring resonator at \(\lambda =1551\,\hbox {nm}\) is about 99.6 % with bandwidth and quality factor values equal to 0.3 nm and 5170. The proposed structure is very sensitive upon the variation of refractive index of total structure and core part of the resonator, such that the refractive index sensitivity to the refractive index of total structure and the resonant ring core is \(\Delta \lambda /\Delta \lambda =3.1\,\hbox {nm}\,/\,0.01\) and \(\Delta \lambda /\Delta \hbox {n}=2.9\,\hbox {nm}\,/\,0.01\), respectively.     

Measurement techniques for monolithic microwave integrated circuits

Introduces the basic technologies that are associated with measurements of monolithic microwave integrated circuits. The use of test fixtures and wafer probe stations at ambient room temperature is reviewed and their role at thermal and cryogenic temperatures is discussed. With the increasing need for performing non-invasive measurements, advances in experimental field probing techniques are explored     

Uniplanar techniques for monolithic microwave integrated circuits

`Uniplanar' techniques have recently been introduced for the design of monolithic microwave integrated circuits (MMICs). The aim of these techniques is to achieve a higher level of integration of circuitry and to overcome the need for through-substrate via holes and the related back-face processing steps. This is achieved by using coplanar waveguide (CPW), slotline, and miniature `thin-film microstrip' transmission-line media as opposed to conventional microstrip. The design and performance of a number of uniplanar MMIC couplers, amplifiers, and other test circuits fabricated using the GEC-Marconi (Caswell) foundry are described     

Large-value monolithic resistors for micropower integrated circuits

The minimum power dissipation of micropower integrated circuits is often limited by the availability of large-value monolithic resistors. Two major types of field-effect resistor structures are examined and an analysis of the primary factors that determine sheet resistance and parasitic capacitance is presented. Resistor tolerance, linearity, and temperature coefficient are briefly discussed. It is shown that resistors with sheet resistances greater than 50 k/spl Omega///spl square/ and parasitic capacitances less than 0.002 pF/k/spl Omega/ can be readily fabricated in a monolithic structure.     

Precision photonic integration for future large-scale photonic integrated circuits

Since the proposal of the concept of photonic integrated circuits (PICs), tremendous progress has been made. In 2005, Infinera Corp. rolled out the first commercial PICs, in which hundreds of optical functions were integrated onto a small form factor chip for wavelength division multiplexing (WDM) systems^[1], then a monolithically integrated 10 × 10 Gb/s WDM chip has been demonstrated, the channel number is ten^[2]. Like ICs, large-scale PICs (LS-PICs) will be sure to be pursued. However, there are still some general challenges associated with LS-PICs. The challenges for III–V (mainly InP) PICs is the semiconductor process, which is not mature for LS-PICs. Up to now, the channel number in commercial III–V WDM PICs by Infinera is still about ten or less. For silicon photonics, the challenge is the silicon based light source. The low cost and mature solution for silicon lasers is still unavailable and only 4 × 25 Gb/s PICs are deployed by Intel Corp. after 18-year R&;D investment. Thus it is still unavailable for practical LS-PICs in the present times.     

InP-based short cavity lasers with 2D photonic crystal mirror

The authors have successfully fabricated in-plane emitting InP-based microlasers with cavity lengths of 600-100 μm. The required high reflectivity mirrors consist of a 2D ΓM-oriented triangular photonic crystal of air rods with a lattice constant of 350 nm. The lasers operate CW at room temperature with a threshold current of 29 mA and output power up to 4 mW for the shortest devices     

Monolithic integrated circuits incorporating InP-based heterostructure barrier varactors

Fully integrated monolithic circuits incorporating InP-based heterostructure barrier varactor (HBV) frequency multipliers have been fabricated via epitaxial liftoff and transfer-substrate techniques onto a quartz substrate. We have obtained a maximum output power of 6 mW at 288 GHz: corresponding to an overall efficiency of 6%. In addition, we have observed a 45-GHz, 3-dB bandwidth centered around 300 GHz for a constant input power of 70 mW.     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

Compact integrated silica wavelength filters

The realization of compact low-loss wavelength filters using two-dimensional integrated optics (2DIO) in a silica-on-silica material system is reported. Two designs suitable for data-communications applications are reported: a 4 /spl times/ 4 channel 6.4-nm channel wavelength spacing device and an 8 /spl times/ 8 channel 3.2-nm channel wavelength spacing device. The devices are fabricated in one deep etch step, and after cleaving the four-channel device has a footprint of 4 /spl times/ 3 min and the eight-channel device 8 /spl times/ 6.5 mm. The average crosstalk of the devices is >22 dB for adjacent channels and 26 dB for nonadjacent channels, and their fiber-to-fiber insertion losses are <12 dB.     

Tantalum oxide capacitors for GaAs monolithic integrated circuits

The performance of a high-yield tantalum oxide capacitor for use in GaAs monolithic microwave integrated circuits is described. The integral metal-insulator-metal sandwich structure is reactively sputter-deposited at low temperatures, compatible with a photoresist lift-off process, on semi-insulating GaAs substrate. Dielectric constants of 20-25 were achieved in the capacitors fabricated. An initial application of this process as an interstage coupling capacitor for a two-stage preamplifier is given.     

Cost-size optima of monolithic integrated circuits

A generalized cost-size relationship is derived for a monolithic circuit consisting of N identical components, taking into account variations in component density, yield, and assembly costs with N. It is intended to reveal cost trends rather than give accurate results for specific cases and deals only with fabrication costs. A yield-area relationship is used which takes into account chip-to-chip variations in defect density. It is found that the ratio (circuit cost per component/cost of discrete transistor) is a minimum at a chip size which is determined primarily by the spot defect density on the device. This optimum chip size lies between approximately 20 and approximately 60 mils square for a wide range of parameter values. State-of-the-art parameter values indicate a potential order of magnitude cost saving in integrated circuits compared with discrete transistors. The minimum value for the cost ratio is in general inversely proportional to the maximum packing density of components on a semiconductor slice and has a limiting value approximately 1/8N, N0being the number of components which can be packed on the chip size normally used for transistors. Arrays of identical logic gates fit the circuit model used quite closely, and the curves indicate that the cost per gate in reasonably densely packed arrays can be less than the cost of a discrete transistor. The results also indicate that when systems requirements make it desirable to include larger numbers of components in one package than the optimum for one monolith, wired-chip schemes are preferable to single monoliths, the optimum chip size being smaller than that for a simple monolith.     

A new air-isolation process for monolithic integrated circuits

A new air-isolation process is described which overcomes many of the problems of existing isolation technologies. The process consists of standard integrated circuit processing except for the p-n junction isolation process which is omitted. After metal mask, the device wafer is glass bonded face down to a supporting silicon wafer. Subsequent backlapping, masking, and mesa etching steps yield an air-isolated integrated circuit. As one application of this technology, the fabrication of a radiation-hardened operational amplifier is described.     

Finite-pole frequencies in monolithic crystal filters

The use of a capacitor in a monolithic crystal filter to obtain finite poles is well known. Several authors have illustrated the variation of the pole frequencies due to the magnitude of the capacitor. The empirical conclusion is that the larger the capacitor, the closer the pole frequencies to the passband or the steeper the skirt. A simple formula is presented for calculating the precise value of a capacitor required to produce prescribed pole frequencies.     

Improved coupling formula for dual monolithic crystal filters

In a new approach, based on the fact that resonance frequencies of monolithic crystal filters are obtained as roots of frequency equations, an improved coupling formula is derived.     

Topology optimised broadband photonic crystal Y-splitter

A planar photonic crystal waveguide Y-splitter that exhibits large-bandwidth low-loss 3 dB splitting for TE-polarised light has been fabricated in silicon-on-insulator material. The high performance is achieved by utilising topology optimisation to design the Y-junction and by using topology optimised low-loss 60/spl deg/ bends. The average excess loss of the entire component is found to be 0.44/spl plusmn/0.29 dB for a 100 nm bandwidth, and the excess loss due to the Y-junction is found to be 0.34/spl plusmn/0.30 dB in a 175 nm bandwidth.     

Compact low-loss monolithic CPW filters using air-gap overlaystructures

In this letter, two types of compact low-loss monolithic coplanar waveguide (CPW) filters using air-gap overlay structures are presented. Vertical stacking in overlay structures offers size reduction. Furthermore, air-gap overlay structures do not require additional dielectric process and are free from dielectric losses. An X-band bandpass filter using air-gap overlaid artificial transmission lines showed 67% size reduction. A stepped-impedance low-pass filter using highly separated metal-air-metal (MAM) capacitors as low-impedance lines achieved not only size but also loss reduction. Small size, low loss, and simple process steps make the air-gap overlay structures very promising for monolithic CPW passive devices such as filters     

Broadband hitless bypass switch for integrated photonic circuits

A new microphotonic hitless switch is proposed. By enabling continuous, uninterrupted transition to a bypass path, it permits tuning of wavelength add-drop filters without disturbing intermediate channels. The scheme comprises two symmetrically actuated, 2 /spl times/ 2 /spl Delta//spl beta/-type optical switches, antisymmetrically cascaded in a balanced Mach-Zehnder configuration, and a /spl pi/ differential phase shift in the interferometer arms. By symmetry, it provides for wavelength-independent hitless operation before, during and after switch reconfiguration, permitting slow switching independent of bit rate. Compact implementations using high-index-contrast microelectromechanical-system (MEMS)-actuated switches are proposed.