ZVS-PWM正激变换器有源箝位磁复位技术的研究

在有源箝位ZVS-PWM正激变换器中,变压器的磁复位技术是其中最关键的一项技术。文章结合仿真和初步的试验结果对有源箝位ZVS-PWM正激变换器的整个工作过程中的能量流动进行分析,总结出使变压器有效磁复位以及开关管ZVS开通的方法。     

交错并联双管正激变换器的分析与设计

本文针对采用无损吸收网络的交错并联式双管正激变换器的工作特点,分析了电路的工作状态、变压器磁复位过程及无损吸收网络的谐振过程,并研制出实验样机,获得的实验结果与理论分析一致,证明了阐述的电路拓扑工作状态的正确性。     

DC—DC正激变换器次级有源箝位电路

提出一种新型DC－DC正激变换器次级有源箝位电路。它一方面将储存于变压器漏感能量无损耗地转移到负载,另一方面有效降低了次级功率二极管电压应力。本文对其一个周期内工作原理及相关理论进行分析,并给出2.8kW DC-DC变换器实验结果及波形。     

采用磁集成技术的有源箝位正激变换器设计

针对3.3 V/10 A低压大电流输出、高功率密度电源模块的设计要求,结合有源箝位正激拓扑理论和磁集成技术,提出采用磁集成技术的有源箝位正激变换器;对变换器中的主变压器和输出电感进行集成,得到高效率、高功率密度的有源箝位正激变换器。     

一种同步整流有源箝位正激变换器的研究

提出一种同步整流有源箝位正激变换器。该变换器是在传统的同步整流有源箝位正激变换器的原边增加一个由箝位电容和电感构成的辅助网络得到。该辅助网络可以使变换器在全负载范围内更容易实现主开关管和辅助开关管的ZVS(Zero-Voltage Switching),副边采用自激式同步整流技术,能进一步提升变换器效率,适用于低压、大电流输出场合。详细分析了变换器的工作原理,搭建了一台8 V/100 W试验样机证明了理论分析的正确性。     

准谐振正激变换器零电压开关设计

准谐振有源箝位正激变换器的有源箝位电路与常规的有源箝位正激变换器的结构类似,但实际工作过程存在许多差异。通过分析准谐振有源箝位正激变换器的工作过程,研究了准谐振有源箝位正激变换器的开关管零电压导通的边界条件,并进行了仿真和实验验证。     

峰值电流控制的磁集成有源箝位正激变换器的小信号模型

文章对采用峰值电流控制的磁集成有源箝位正激变换器进行了小信号分析。建立的模型不但包括复位电路和斜坡补偿电路部分,还包括集成磁件部分。最后给出了补偿器设计原则,完成了闭环设计。     

基于LM5025的有源箝位反激变换器的前馈控制

在有源箝位反激变换器负载基本恒定的情况下采用前馈控制既可以减小变换器体积,又可降低变换器的成本。文中在分析有源箝位反激变换器工作原理的基础上,结合LM5025器件的前馈控制特性,深入研究了基于LM5025的有源箝位反激变换器前馈控制的实现方案,设计了前馈控制电路的参数,完成了有源前馈反激变换器电路设计。在此基础上进行了实验研究,实验结果证明了有源箝位反激变换器前馈控制的有效性和实用性。     

一种正激变换器的输出过流保护电路

设计了一种适用于有源箝位正激变换器的输出过流保护电路。通过分析峰值电流模下正激变换器的反馈与控制原理,实现了过流保护电路可控制正激系统在五种不同工作模式下切换。该技术通过调节片外电阻RCS,实现可编程过流阈值自主设定。同时通过调节片外电容CRES,实现可编程过流时域响应快慢。该电路基于0.18 μm BCD工艺进行了仿真与流片测试,实际测试结果表明,系统发生过流时,可以实现良好的过流保护功能。     

双管正激变换器的工作原理与FOM

本文介绍了双管正激变换器的工作原理与FOM,并且论述了双管正激变换器与PFC转换器的对比、FOM和功率耗损。本文网络版地址：http：//www.eepw.com.cn/article/276366.htm     

A double ZVS-PWM active-clamping forward converter: analysis,design, and experimentation

This paper presents an isolated DC-DC converter based on two ZVS-PWM active-clamping forward converters connected in series and coupled by a single high-frequency transformer. The proposed converter features no switching losses from no-load to full-load operation and low conduction losses. This converter is suitable for high input voltage (>400 VDC) and high power applications. Operation principles, theoretical analysis and design example, are presented, as well as experimental results taken from a 3 kW laboratory prototype     

电流模块交错并联的光纤激光器电源研制

提出以4路电流模块LTM4601并联的方式实现低压大电流输出的解决方案,其关健是并联模块间的均流,设计以4路交错90°的波形分别同步4路模块的波形交错技术实现.设计的独特之处在于并联电源系统输出电流母线引入电流反反馈以实现输出电流值的控制.基于大电流印刷电路板(PCB)设计得到电源样机,其实验结果与设计目标基本相符.实...     

电压反馈型双管正激变换器的非线性

对工作于电流连续模式下的电压反馈型双管正激变换器,在一定的假设前提下建立小信号模型来研究变压器一次绕组和二次绕组匝数比不同时的非线性.利用仿真软件MATLAB/Simulink,建立仿真模型进行计算机仿真,得到滤波电感电流波形,观察到改变变压器匝数比存在非线性现象,验证了理论分析结果.     

Design and implementation of a novel synchronous-rectifier forward converter with improved performance

This article proposes two new methods for improving the performance of a synchronous-rectifier forward converter. A synchronous-rectifier converter produces a reverse current in the inductor due to the bidirectional characteristic of MOSFETs while the converter is turned off. This reverse current causes voltage spikes which may damage the power devices. This article proposes two methods to reduce the voltage spikes: method 1 and method 2. Method 1 uses the enable signal detection method. An enable signal is generated from the remote control of the system when the main power is turned off. Then, the proposed circuit of method 1 turns off the free-wheeling switch before the reverse current is produced. As a result, the voltage spike can be avoided. Method 2 uses a transformer winding to detect the turn-off time of the input power. Then, the circuit turns off the free-wheeling switch to break the resonant loop and end the reverse current. The cost analysis of method 1 and 2 is included. In addition, several experimental results are provided to validate the correctness and feasibility of the theoretical analysis.     

Small‐block interleaving for low‐delay cross‐packet forward error correction over burst‐loss channels

By adding the redundant packets into source packet block, cross‐packet forward error correction (FEC) scheme performs error correction across packets and can recover both congestion packet loss and wireless bit errors accordingly. Because cross‐packet FEC typically trades the additional latency to combat burst losses in the wireless channel, this paper presents a FEC enhancement scheme using the small‐block interleaving technique to enhance cross‐packet FEC with the decreased delay and improved good‐put. Specifically, adopting short block size is effective in reducing FEC processing delay, whereas the corresponding effect of lower burst‐error correction capacity can be compensated by deliberately controlling the interleaving degree. The main features include (i) the proposed scheme that operates in the post‐processing manner to be compatible with the existing FEC control schemes and (ii) to maximize the data good‐put in lossy networks; an analytical FEC model is built on the interleaved Gilbert‐Elliott channel to determine the optimal FEC parameters. The simulation results show that the small‐block interleaved FEC scheme significantly improves the video streaming quality in lossy channels for delay‐sensitive video. Copyright © 2013 John Wiley & Sons, Ltd.     

A new family of ZVS-PWM active-clamping DC-to-DC boost converters:analysis, design, and experimentation

The purpose of this paper is to introduce a new family of zero-voltage switching (ZVS) pulse-width modulation (PWM) active-clamping DC-to-DC boost power converters. This technique presents ZVS commutation without additional voltage stress and a significant increase in the circulating reactive energy throughout the power converters. So, the efficiency and the power density become advantages when compared to the hard-switching boost power converter. Thus, these power converters may become very attractive in power factor correction applications. In this paper, the complete family of boost power converters is shown, and one particular circuit, taken as an example, is analyzed, simulated and experimented. Experimental results are presented, taken from a laboratory prototype rated at 1600 W, input voltage of 300 V, output voltage of 400 V, and operating at 100 kHz. The measured efficiency at full load was 98%, and the power converter kept an efficiency up to 95% from 17% to 100% of full load, without additional voltage and current stresses     

Analysis and Implementation of Dual-ZCS forward DC/DC Converter

As the switching frequency of switch mode power supply (SMPS) increases, the original working mode, such as pulse width modulate (PWM) is not compatible. So, many researches start to investigate new soft switching technic[1~3]. Soft switches not only have the advantages of lower switching loss, higher working frequencies and smaller volume, but also introduce little electromagnetic interference than hard switches. The combination of dual-switch forward topology and soft switch technology ca…     

交错并联式BOOST电路的Pspice仿真分析

文中研究基于Pspice软件的交错并联BOOST变换器的拓扑结构,并对其建立仿真模型,进而延伸到N个相同的BOOST拓扑结构的并联,从中分析了此种拓扑结构的优点,进而得出此种拓扑结构适于在功率因数校正电路中应用的结论。     

基于交织的二元及四元完备序列和序列偶的构造方法

基于交织技术,提出了三类二元及四元完备序列和序列偶的构造方法。分别利用二元完备序列、二元完备互补序列对和二元完备序列偶作为初始序列,通过合理设计带符号移位序列,基于交织获得了不同的二元及四元完备序列和序列偶。这些构造方法均可不断递归地进行,从而获得更多具有新参数的完备序列及完备序列偶。该方法通过引入带符号的移位序列,在一定程度上改善了目标序列的相关性能,为序列的构造提供了新的思路。     

一种新颖的恒流源并联方法

介绍一种新颖的恒流源并联方法。实验中选用了6台采用双管正激交错并联电路设计的恒流源进行并联,单台电源的最大功率输出为60 V 100 A。使用该方法并联后,输出电流可在480 A～580 A任意可调。实验结果证明,该并联方法具有电路结构简单、易实现、稳定度高等优点。