高压BiCMOS工艺中耗尽型NJFET的设计与应用

摘 要：本文提出了一种新型的兼容高压BiCMOS工艺的耗尽型NJFET,并实际研制了一种四路12位数模转换器。研制的NJFET夹断电压-1.5V,击穿电压17V;带轻掺杂漏区的高压NMOS管开启电压1.0V,击穿电压35V;齐纳二极管的正向电压5.5V。使用该耗尽型NJFET及其兼容工艺研制的四路12位数模转换器的基准温度系数为±25ppm/℃,微分误差小于±0.3LSB,线性误差小于±0.5LSB,还可以广泛应用于其他高压数模/模数转换器的研制。     

一种新型硅基恒流二极管的特性研究

提出了一种新型硅基环状分布垂直沟道恒流二极管,包括并联的结型场效应晶体管和PIN整流管。建立了器件的数值模型,并利用SILVACO TCAD仿真工具对器件的恒定电流值、击穿电压等特征参数进行模拟。结果显示,该器件工作于正向时,恒流效果好,开启电压约为3 V,击穿电压可达140 V;该器件工作在反向时,表现出良好的整流特性,开启电压约为0.8 V。     

结型场效应晶体管的主要参数的探讨

本文讨论了结型场效应晶体管的几个主要参数，找出影响它们的主要因素。     

一种5位10 GHz SiGe BiCMOS比较器

SiGe BiCMOS提供了性能极其优异的异质结晶体管(HBT),其ft超过70 GHz,β>120,并具有高线性、低噪声等特点,非常适合高频领域的应用。基于SiGe BiCMOS工艺,提出了一种高性能全差分超高速比较器。该电路由宽带宽前置放大器和改进的主从式锁存器组成,采用3.3 V单电压源,比较时钟超过10 GHz,差模信号电压输入量程为0.8 V,输出差模电压0.4 V,输入失调电压约2.5 mV;工作时钟10 GHz时,用于闪烁式A/D转换器可以达到5位的精度。     

结型场效应晶体管的主要参数的探讨

本文讨论了结型场效应晶体管的几个主要参数 ,找出影响它们的主要因素     

一种8 Bit 10 GHz SiGe BiCMOS比较器

SiGe BiCMOS提供了性能极其优异的HBT（异质结晶体管）,其ft超过70 GHz,β〉120,高线性,低噪声,非常适合高频领域应用。本文基于SiGe BiCMOS工艺。提出了一种高性能全差分超高速比较器,它由宽带宽前置放大器、改进的主从式锁存器组成。采用3．3v单电压源,比较时钟超过10GHz,差模信号电压输入量程为0．8V,输出差模电压为0．4V,输入失调电压约2．5mV,用于8位两步闪烁式AID转换器。     

基于场效应晶体管的太赫兹探测器中天线设计的一种有效方法

在场效应晶体管太赫兹探测器中,合理的天线设计可以增强晶体管和太赫兹波之间的耦合效率,从而提高太赫兹探测器的响应度.提出一种基于晶体管栅极边缘沟道电场的仿真来设计平面天线的方法.这种方法尤其适用于太赫兹波段晶体管输入阻抗不容易得到的情况.通过流片完成的基于氮化镓高电子迁移率晶体管的太赫兹探测器的响应度测试证实了这种方法的有效性.集成碟形天线和双偶极子天线的太赫兹探测器最大响应度分别在170.7 GHz(1568.4 V/W)和124.3 GHz(1047.2 V/W)频点处测得,这个测试结果接近基于晶体管栅极边缘沟道电场的仿真结果.     

一种沟槽型SGTMOSFET终端结构

为了在提升终端耐压的同时减少终端的使用面积,基于屏蔽栅沟槽型MOSFET (shielded gate trench MOSFET,简称SGTMOSFET)设计了一种沟槽型终端。通过Sentaurus TCAD软件对终端结构进行仿真,仅改变沟槽和P型环参数,最终使终端的耐压达到了135V,有效终端长度仅为18.5μm。此终端结构适用于中低压领域,且在SGTMOSFET元胞工艺步骤的基础上仅增加了一层掩膜,终端结构工艺和元胞工艺兼容,易于实现。     

SJ-LDMOST中的衬底辅助耗尽效应

本文分析了SJ-LDMOST中衬底辅助耗尽效应的产生机理。文中将业界消除衬底辅助耗尽效应的主要方法分成两类,并提出消除衬底辅助耗尽效应的途径。     

一种SiGe BiCMOS高速PNP器件的设计

设计了一种适用于SiGe BiCMOS工艺的低成本、高性能垂直结构PNP器件.基于仿真结果,比较了不同发射区和基区制作方法对器件特性的影响.在确定器件结构和制作工艺的基础上,进一步优化了器件特性.基于仿真得到的工艺条件所制作的PNP器件,其特性与仿真结果基本一致.最终优化的PNP器件的电流增益为38,击穿电压大于7V,特征频率为10 GHz.该PNP晶体管改善了横向寄生硅基区PNP晶体管的性能,减少了垂直SiGe基区PNP晶体管工艺的复杂性,采用成本低廉的简单工艺实现了优良的器件性能.     

Design and application of a depletion-mode NJFET in a high-voltage BiCMOS process

A novel depletion-mode NJFET compatible high-voltage BiCMOS process is proposed and experimentally demonstrated with a four-branch 12-bit DAC(digital-to-analog converter).With this process,an NJFET with a pinch-off voltage ofabout-1.5 V and a breakdown voltage of about 16 V,an NLDDMOS(N-type lightly-dosed-drain in MOS) with a turn-on voltage of about 1.0 V and a breakdown voltage of about 35 V,and a Zener diode with a reverse voltage of about 5.6 V were obtained.Measurement results showed that the conver...     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

A BiCMOS wired-OR logic

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and the supply voltage was 3.3 V. The BiCMOS wired-OR logic was also determined to be the fastest of the four when the fan-out number was below 20 and the number of inputs was eight. In addition, the speed was more than twice as faster when the fan-out number was less than 10. The BiCMOS wired-OR logic was applied to a 64-b 2-stage carry look-ahead adder, and was fabricated with a 0.5-μm BiCMOS process technology. A critical path delay time of 3.1 ns from an input to a sum output was obtained at the supply voltage of 3.3 V. This is 35% faster than that of conventional BiCMOS adders     

一种BiCMOS过温保护电路

在分析现有过温保护电路的基础上,针对它们电路结构复杂、功耗较高、工作电压高等缺点提出了一种用于集成电路内部的采用BiCMOS工艺的过温保护电路,电路结构简单、功耗较低、工作电压低、抗干扰能力强,对温度的迟滞特性避免了热振荡对芯片带来的危害。采用0．6μm BiCMOS工艺的HSPICE仿真结果表明,该电路对因电源电压、和工艺参数变化而引起的温度迟滞特性的漂移具有很强的抑制能力。     

A 2.5-V BiCMOS comparator with current-mode interpolation

A high-speed latched comparator based on a current-mode architecture is presented. It achieves a sampling speed of 150 MS/s at 2.5 V supply, with a power consumption lower than conventional schemes. Its very low kickback noise makes it especially suitable for differential analog-to-digital converters (ADCs). Moreover, it supports precise 2X interpolation in current mode at full clock speed, allowing a further reduction of the ADC power consumption. The comparator was implemented in a 0.8 μm BiCMOS technology     

一种BiCMOS过热保护电路

提出了一种集成于电源管理芯片内部的过热保护电路。采用0．6μm BiCMOS工艺参数，对电路进行模拟仿真，并与先前提出的过热保护电路进行比较。结果表明，该电路具有关断和开启阈值点的准确性强、对温度灵敏度高、超低静态电流和低功耗等特点。     

一种新颖的BiCMOS高精度LDO线性稳压电路

设计了一种改进结构的用于锂离子和锂聚合物电池充电管理芯片的高精度、宽电源电压范围LDO线性稳压电路,电路采用0.8μm N阱BiCMOS高压工艺制作。Hspice仿真结果表明,在温度从-20℃到100℃变化时,其温度系数约为±28 ppm/℃;电源电压从4.5 V到25 V变化时,最坏情况下其线性调整率为0.038 mV/V;负载电流从0到满载2 mA变化时,其负载调整率仅为1.28 mV/mA。     

A BiCMOS speech circuit with only two external components

A telephone chip that performs all the basic functions of a speech circuit using only two external components is reported. Precision filtering based on switched-capacitor (SC) techniques is used to implement on-chip impedance termination, hybrid with sidetone cancellation, and DC characteristics starting from a single 1% external resistor. A new low-drop on-chip voltage supply generator derived from the line using an external storage capacitor is also realized. Better than 33-dB impedance matching and more than 30-dB sidetone cancellation is achieved without any external trimming. The TX linearity is better than 50 dB up to 4.4 V_p-p on the line. The chip has an active area of approximately 2.6 mm² and draws 1.5 mA of quiescent current     

A BiCMOS PLL-based data separator circuit with high stability andaccuracy

A data separator that can work in Winchester disk drives at a read/write speed of up to 30 Mb/s is described. To realize high stability and accuracy in reproducing data in high-speed transfers, a digital synchronization field detector and an analog dual-mode phase-locked loop (PLL) that has a phase detector which has constant gain in the data field, independent of pattern, are used. The dual-mode analog PLL has a wide decode margin, locks up quickly, and operates stably without being affected by the frequency deviation of data. The digital sync field detector is adjustment-free and detects sync fields very accurately. The IC incorporates a RLL 2-7 code encoder/decoder and a write compensator. Use of the 2-μm BiCMOS process keeps the total power consumption as low as 400 mW even at the high transfer rate of 30 Mb/s