Read disturb in flash memories: reliability case

It is known that program/erase cycling of Flash memories induces a degradation of the tunnel oxide insulating property usually referred to as Stress-Induced Leakage Current (SILC). An issue related to SILC is the read disturb, affecting cells in an addressed word-line, which can cause electron injection through tunnel oxide in the floating gate of erased cells during read operation. Read disturb can also be present in Flash memory with a weak tunnel oxide quality: aim of this paper is to discuss in detail the effect of this read disturb phenomena. Cell Failure Density (CDF) extrapolation from experimental data using statistical method is able to estimate defect probability and application’s failure rate for both SILC and weak tunnel oxide quality cases.     

Simulating oscillators using SPICE

SPICE generation of the output signals from electronic oscillator circuits is obtained by transient analysis. Simulation success is software specific and depends upon how the transient analysis function is configured. Different tricks, which are oscillator configuration specific, may be applied to achieve simulation output. In the final analysis, one must remember that simulation is not a complete and full replacement for circuit construction and testing. Accurate analysis is given for resonant or relaxation circuits     

A study of hot-hole injection during programming drain disturb in flash memories

Program disturbs in NOR-type Flash arrays significantly degrade the tunnel oxide by hot-hole injection (HHI) induced by band-to-band tunneling at the drain overlap. This paper provides a comprehensive experimental and modeling analysis of HHI in Flash memories under program-disturb conditions. Carrier-separation measurements on arrays of Flash memories with contacted floating-gate (FG) allows for a direct investigation of hole-initiated impact ionization and HHI. A Monte Carlo (MC) model is used to simulate carrier multiplication and injection into the FG. After validating the MC model against experimental data for both secondary electron generation and HHI, the model is used to provide further insight into the hole-injection mechanism.     

Novel program versus disturb window characterization for split-gate flash cell

In this letter, a new methodology for program versus disturb window characterization on split gate flash cell is presented for the first time. The window can be graphically illustrated in V/sub wl/ (word-line)-V/sub ss/ (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program bias variations. This methodology was successfully implemented in 0.18-/spl mu/m triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.     

SPICE compatible analytical electron mobility model for biaxial strained-Si-MOSFETs

This paper describes an analytical model for bulk electron mobility in strained-Si layers as a function of strain.Phonon scattering,columbic scattering and surface roughness scattering are included to analyze the full mobility model.Analytical explicit calculations of all of the parameters to accurately estimate the electron mobility have been made.The results predict an increase in the electron mobility with the application of biaxial strain as also predicted from the basic theory of strain physics of metal oxide semiconductor(MOS) devices.The results have also been compared with numerically reported results and show good agreement.     

A unified SPICE compatible average model of PWM converters

A simple, unified, and topology-independent model of basic pulse-width modulated (PWM) power converters is developed using the switched inductor approach presented by S. Ben-Yaakov (1989). The model is compatible with SPICE or other similar general-purpose electronic circuit simulators. It can be used to simulate DC, small signal, and transient behavior of PWM converters operating in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). During simulation, the model automatically follows the CCM and DCM operation, with fewer convergence problems compared to previous simulation models. An effective measurement technique using the HP3562A dynamic signal analyzer (DSA) is presented and applied to compare simulation runs with experimental data. The two were found to be in good agreement     

A statistical model for SILC in flash memories

The reliability of flash memories is strongly. limited by the stress-induced leakage current (SILC), which leads to accelerated charge-loss phenomena in a few anomalous cells. Estimating the reliability of large flash arrays requires that physically-based models for the statistical distribution of SILC are developed. In this paper, we show a physical model for the leakage mechanism in thin oxides, which is able us to explain the anomalous leakage-conduction in tail cells. The physical model is then used for a quantitative evaluation of the SILC distribution in large flash arrays. The new model can reproduce the statistics of SILC for a wide range of tunnel-oxide thickness, and can provide a straightforward estimation of the reliability for large flash arrays.     

A SPICE compatible subcircuit model for lateral bipolar transistorsin a CMOS process

This paper describes a SPICE compatible subcircuit model of a lateral pnp transistor, which was fabricated in a 0.6 μm CMOS process. The extraction of a dc parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. The SPICE Gummel-Poon model does not predict the substrate current accurately. This paper proposes a method which involves the use of a subcircuit incorporating three SPICE Gummel-Poon models [representing one lateral and two parasitic vertical bipolar junction transistors (BJT's)]. The development of this model, its implementation and the results obtained are outlined and discussed. This circuit model is SPICE compatible and can thus be used in commercial simulators. The model provides good agreement over a wide range of measured dc data including substrate current prediction     

Analytical percolation model for predicting anomalous charge loss in flash memories

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.     

用存储器映射的方法实现片外FLASH的擦写

提出一种通过存储器地址映射的方式实现对DSP嵌入式系统片外FLASH擦写的方法。文中介绍的程序有一定参考价值。     

Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted (near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain (V_ds) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.     

Charging simulations in nanocrystal quantum flash memories

The comprehension of the charging of a floating gate composed of nanocrystals (NCs) in a non-volatile flash memory is a real challenge. A few electrons tunnel from the channel of a metal-oxide-semiconductor transistor into the two-dimensional array of nanocrystals.A realistic three-dimensional model is proposed for electron tunneling into the floating gate. The energy subbands of the channel are explicitly included, together with the doping density. The model is solved thanks to a finite element method.Therefore many simulations can be carried out to better understand the relation between the tunneling times for charging a single NC, or the whole NC floating gate, and the geometrical parameters for example. Moreover a detailed statistical study concerning the dispersion of the relevant parameters can be led, helping the experimentalists to determine the optimal operating conditions of quantum flash memories.     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

High-voltage management in single-supply CHE NOR-type flash memories

In a flash memory, a number of voltage levels different from V/sub DD/ are needed to perform the required operations (read, program, and erase) on the array cells. In the case of single-supply memory devices, voltages higher than V/sub DD/ as well as negative voltages, which are referred to as high voltages (HVs), must be produced on-chip. This paper aims at giving the reader an overview of how HVs are generated and managed in single-supply NOR-type flash memories programmed by channel hot-electron injection. Both schemes used for conventional (i.e., bilevel) memory devices and schemes designed to meet multilevel memory requirements are addressed.     

Statistical profiling of SILC spot in flash memories

A new experimental technique for evaluating the position of the oxide weak spot responsible for the stress-induced leakage current (SILC) in flash memories is presented. The oxide field along the channel is modified by drain biasing, and the gate current is then monitored. The position of the leakage spot can be determined by the shift in the gate current-voltage (I-V) characteristics. Experimental results on flash memory arrays reveal a strong localization of SILC in correspondence of the drain junction, due to the cooperation effects of program/erase (P/E) operations. The technique can be used to optimize the P/E conditions for maximum device reliability.     

Unified SPICE compatible model for large and small-signal envelope simulation of linear circuits excited by modulated signals

The envelope-simulation method, developed earlier for large-signal simulation [time domain (TRAN)] is extended to include small-signal envelope simulation (ac) and dc sweep simulation (steady state for a range of carrier frequencies). The model is derived for amplitude modulation (AM), frequency modulation (FM), and phase modulation (PM) modulation schemes and is demonstrated on a piezoelectric transformer circuit. The model is based on the equivalent circuit approach and can be run on any modern electronic circuit simulator. An excellent agreement was found between the simulation results according to the new unified envelope model, full simulation, and experimental results.     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

An asymmetric two-side program with one-side read (ATPOR) device for MultiBit per cell MLC nitride-trapping flash memories

An asymmetric two-side program with one-side read (ATPOR) Flash memory device is proposed. In this nitride-trapping device, the interaction of stored charges in the two sides (second-bit effect) is utilized to achieve multilevel cell (MLC) V/sub t/ levels with the advantages of relatively small total charge. The small total charge can enhance both programming and erasing efficiency. The ATPOR device with programming and erasing times within 100 ns and 40 /spl mu/s are demonstrated. Excellent read disturb immunity of ATPOR device can provide high scaling capability. In addition, good data retention and P/E cycling endurance and reliability are achieved. For 2-bit/cell and 3-bit/cell MLC applications, the ATPOR device with tight level distributions less than 100 mV is illustrated.     

Characterization of hot-hole injection induced SILC and relateddisturbs in flash memories

In this paper, we have proposed a new method for the study of disturb failure mechanisms caused by stress induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual components of SILC due to either carrier charging/discharging in the oxide or the positive charge/trap assisted electron tunneling into the floating gate. In addition, the present method is very sensitive with capability of measuring ultralow current (<10^-19 A). Results show that, at low oxide field, the disturb is mainly contributed by the so-called charging/discharging of carriers into/from the oxide due to the capacitance coupling effect. While at high oxide field, the positive charge/trap assisted electron tunneling induced floating-gate charge variation is the major cause of disturb failure