应变SiGe p 型金属氧化物半导体场效应管栅电容特性研究

由于台阶的出现, 应变SiGe p型金属氧化物半导体场效应管 (pMOSFET) 的栅电容特性与体Si器件的相比呈现出很大的不同, 且受沟道掺杂的影响严重. 本文在研究应变SiGe pMOSFET器件的工作机理及其栅电容C-V 特性中台阶形成机理的基础上, 通过求解器件不同工作状态下的电荷分布, 建立了应变SiGe pMOSFET栅电容模型, 探讨了沟道掺杂浓度对台阶的影响. 与实验数据的对比结果表明, 所建立模型能准确反映应变SiGe pMOSFET器件的栅电容特性, 验证了模型的正确性. 该理论为Si基应变金属氧化物半导体(MOS)器件的设计制造提供了重要的指导作用, 并已成功应用于Si基应变器件模型参数提取软件中, 为Si基应变MOS的仿真奠定了理论基础. 关键词： 应变SiGe pMOSFET 栅电容特性 台阶效应 沟道掺杂     

辐照下背栅偏置对部分耗尽型绝缘层上硅器件背栅效应影响及机理分析

基于部分耗尽型绝缘层上硅（SOI）器件的能带结构,从电荷堆积机理的电场因素入手,为改善辐照条件下背栅Si/SiO₂界面的电场分布,将半导体金属氧化物（MOS）器件和平板电容模型相结合,建立了背栅偏置模型.为验证模型,利用合金烧结法将背栅引出加负偏置,对NMOS和PMOS进行辐照试验,得出:NMOS背栅接负压,可消除背栅效应对器件性能的影响,改善器件的前栅I-V特性;而PMOS背栅接负压,则会使器件的前栅I-V性能恶化.因此,在利用背栅偏置技术改善SOI/NMOS器件性能的同时,也需要考虑背栅偏置对PMOS的影响,折中选取偏置电压.该研究结果为辐照条件下部分耗尽型SOI/MOS器件背栅效应的改善提供了设计加固方案,也为宇航级集成电路设计和制造提供了理论支持.     

单轴应变硅N沟道金属氧化物半导体场效应晶体管电容特性模型

电容特性模型是单轴应变硅金属氧化物半导体场效应晶体管(Si MOSFET)和电路进行瞬态分析、交流小信号分析、噪声分析等的重要基础. 本文首先建立了单轴应变Si NMOSFET 的16 个微分电容模型, 并将微分电容的仿真结果与实验结果进行了比较, 验证了所建模型的正确性. 同时对其中的关键性栅电容C_gg 与应力强度、偏置电压、沟道长度、栅极掺杂浓度等的关系进行了分析研究. 结果表明, 与体硅器件相比, 应变的引入使得单轴应变Si NMOSFET器件的栅电容增大, 随偏置电压、沟道长度、栅极掺杂浓度的变化趋势保持不变.     

亚100 nm应变Si/SiGe nMOSFET阈值电压二维解析模型

本文基于二维泊松方程,建立了适用于亚100 nm应变Si/SiGe nMOSFET的阈值电压理论模型.为了保证该模型的准确性,同时考虑了器件尺寸减小所导致的物理效应,如短沟道效应,量子化效应等.通过将模型的计算结果与二维器件模拟器ISE的仿真结果进行对比分析,证明了本文提出的模型的正确性.最后,还讨论了亚100 nm器件中常规工艺对阈值电压的影响.该模型为亚100 nm小尺寸应变Si器件的分析设计提供了一定的参考. 关键词： 亚100nm 应变Si/SiGe nMOSFET 二维表面势 阈值电压     

应变Si n型金属氧化物半导体场效应晶体管电荷模型

基于应变Si/SiGe器件结构,本文建立了统一的应变Si NMOSFET电荷模型.该模型采用电荷作为状态变量,解决了电荷守恒问题.同时采用平滑函数,实现了应变Si NMOSFET端口电荷及其电容,从亚阈值区到强反型区以及从线性区到饱和区的平滑性,解决了模型的连续性问题.然后采用模拟硬件描述语言Verilog-A建立了电容模型.通过将模型的仿真结果和实验结果对比分析,验证了所建模型的有效性.该模型可为应变Si集成电路分析、设计提供重要参考.     

应变Si/(001)S1－xGex本征载流子浓度模型

利用应变Si CMOS技术提高载流子迁移率是当前研究发展的重点,本征载流子浓度是应变Si材料的重要物理参数,也是决定应变Si器件电学特性的重要参量.本文基于K.P理论框架,从分析应变Si/（001）Si_1-xGe_x材料能带结构出发,详细推导建立了300K时与Ge组分（x）相关的本征载流子浓度模型.该数据量化模型可为Si基应变器件物理的理解及器件的研究设计提供有价值的参考. 关键词： 应变Si 有效态密度 本征载流子浓度     

金属氧化物半导体场效应管热载流子退化的1/fγ噪声相关性研究

研究了金属氧化物半导体(MOS)器件在高、中、低三种栅压应力下的热载流子退化效应及其1/fγ噪声特性.基于Si/SiO2界面缺陷氧化层陷阱和界面陷阱的形成理论,结合MOS器件1/f噪声产生机制,并用双声子发射模型模拟了栅氧化层缺陷波函数与器件沟道自由载流子波函数及其相互作用产生能级跃迁、交换载流子的具体过程.建立了热载流子效应、材料缺陷与电参量、噪声之间的统一物理模型.还提出了用噪声参数Sfγ表征高、中、低三种栅应力下金属氧化物半导体场效应管抗热载流子损伤能力的方法.根据热载流子对噪声影响的物理机制设计了实验并验证这个模型.实验结果与模型符合良好.     

氮化硅膜致小尺寸金属氧化物半导体晶体管沟道单轴应变物理机理

应力作用下MOS性能可显著提升, 小尺寸MOS沟道中单轴应力的引入可通过在MOS表面覆盖淀积SiN膜实现. 虽然该工艺已广泛应用于MOS性能的提升, 但有关SiN膜致MOS沟道应力的产生机理、作用机理, 以及SiN膜结构与MOS沟道应力类型关联性等方面的研究仍需深入探讨. 本文基于ISE TCAD仿真, 提出了分段分析、闭环分析和整体性分析三种模型. 通过对Si MOS源、栅、漏上多种SiN膜淀积形式的深入分析, 揭示了SiN膜致MOS 沟道应力产生与作用物理机理. 研究发现: 1) “台阶”结构是SiN膜导致MOS沟道应变的必要条件; 2) SiN膜具有收缩或者扩张的趋势, SiN膜主要通过引起MOS源/漏区域Si材料的形变, 进而引起沟道区Si材料发生形变; 3)整体SiN膜对沟道的应力等于源/漏上方SiN膜在源/漏所施加的应力、“闭环结构”对沟道内部所施加的应力以及SiN膜的完整性在沟道产生的应力的总和. 本文物理模型可为小尺寸MOS工艺制造, 以及MOS器件新型应力引入的研究提供有价值的参考.     

应变Si/(001)Si1-xGex电子迁移率

依据离化杂质散射、声学声子散射和谷间散射的散射模型,在考虑电子谷间占有率的基础上,通过求解玻尔兹曼方程计算了不同锗组分下,不同杂质浓度时应变Si/(001)Si_1-xGe_x的电子迁移率.结果表明:当锗组分达到0.2时,电子几乎全部占据Δ₂能谷;低掺杂时,锗组分为0.4的应变Si电子迁移率与体硅相比增加约64%;对于张应变Si NMOS器件,从电子迁移率角度来考虑不适合做垂直沟道.选择相应的参数,该方 关键词： 电子谷间占有率 散射模型 锗组分 电子迁移率     

应变Si沟道nMOSFET阈值电压模型

在研究分析弛豫SiGe衬底上的应变Si 沟道nMOSFET纵向电势分布的基础上,建立了应变Si nMOSFET阈值电压模型,并利用该模型对不同的器件结构参数进行仿真,获得了阈值电压与SiGe层掺杂浓度和Ge组分的关系、阈值电压偏移量与SiGe层中Ge组分的关系、阈值电压与应变Si层掺杂浓度和厚度的关系. 分析结果表明：阈值电压随SiGe层中Ge组分的提高而降低,随着SiGe层的掺杂浓度的提高而增大;阈值电压随应变Si层的掺杂浓度的提高而增大,随应变Si层厚度增大而增大. 该模型为应变Si 器件阈值电压设计 关键词： 应变硅 阈值电压 电势分布 反型层     

Memory characteristics of platinum nanoparticle-embedded MOS capacitors

The capacitance characteristics of platinum nanoparticle (NP)-embedded metal–oxide–semiconductor (MOS) capacitors with gate Al₂O₃ layers are studied in this work. The capacitance versus voltage (C–V) curves obtained for a representative MOS capacitor exhibit flat-band voltage shifts, demonstrating the presence of charge storages in the platinum NPs. The counterclockwise hysteresis and flat-band voltage shift, observed from the C–V curves imply that electrons are stored in a floating gate layer consisting of the platinum NPs present between the tunneling and control oxide layers in the MOS capacitor and that these stored electrons originate from the Si substrate. Moreover, the charge remains versus time curve for the platinum NP-embedded MOS capacitor is investigated in this work.     

Analytical modeling and simulation of subthreshold characteristics of back-gated SSGOI and SSOI MOSFETs: A comparative study

The Silicon–Germanium-on-Insulator (SGOI) and Silicon-on-Insulator (SOI) based MOS structures are spearheading the strained-Si technology. The present work compares the subthreshold characteristics of two short-channel back-gated (BG) strained-Si-on-SGOI (SSGOI) and BG strained-Si-on-Insulator (SSOI) MOSFETs, and provides some solutions to overcome the degradation in subthreshold characteristics with the unrelenting downscaling of the devices. Subthreshold behaviors of the MOS structures are based on surface potential model which is determined by solving the 2D Poisson's equation with suitable boundary conditions by evanescent mode analysis for both of the MOS structures. The closed form expressions for threshold voltage, subthreshold current and subthreshold swing have been derived for symmetrical as well as independent gate operation (IGO). In addition, the Electrostatic integrity (EI) factors for SSOI and SSGOI MOS structures have been estimated and compared with Double-Gate (DG) MOSFET. The numerical simulation results, obtained by ATLAS?, a 2D device simulator from Silvaco, have been used to assess the validity of the models.     

Study of total ionizing dose radiation effects on enclosed gate transistors in a commercial CMOS technology

This paper studies the total ionizing dose radiation effects on MOS (metal-oxide-semiconductor) transistors with normal and enclosed gate layout in a standard commercial CMOS (compensate MOS) bulk process. The leakage current, threshold voltage shift, and transconductance of the devices were monitored before and after $\gamma $-ray irradiation. The parameters of the devices with different layout under different bias condition during irradiation at different total dose are investigated. The results show that the enclosed layout not only effectively eliminates the leakage but also improves the performance of threshold voltage and transconductance for NMOS (n-type channel MOS) transistors. The experimental results also indicate that analogue bias during irradiation is the worst case for enclosed gate NMOS. There is no evident different behaviour observed between normal PMOS (p-type channel MOS) transistors and enclosed gate PMOS transistors.     

Enhanced ESD properties of GaN-based light-emitting diodes with various MOS capacitor designs

High electrostatic discharge (ESD) protection of GaN-based light-emitting diodes (LEDs) has been developed using a metal–oxide semiconductor (MOS) capacitor. This structure is realized by adopting various metal electrode patterns. The MOS capacitor can be implemented by extending the metal line directly from the p-type electrode to the top surface of an SiO₂-capped n-GaN layer near the vicinity of the n-type electrode. By connecting a MOS capacitor in parallel with the GaN-based LED, the negative ESD strike could be significantly increased from 385 to 1075 V of human body mode (HBM).     

高迁移率Ge沟道器件研究进展

高迁移率Ge沟道器件由于其较高而且更对称的载流子迁移率, 成为未来互补型金属-氧化物-半导体(CMOS) 器件极有潜力的候选材料. 然而, 对于Ge基MOS器件, 其栅、源漏方面面临的挑战严重影响了Ge基MOS 器件性能的提升, 尤其是Ge NMOS器件. 本文重点分析了Ge基器件在栅、源漏方面面临的问题, 综述了国内外研究者们提出的不同解决方案, 在此基础上提出了新的技术方案. 研究结果为Ge基MOS 器件性能的进一步提升奠定了基础.     

Generation of excess minority carriers in mos devices due to gamma irradiation

The effect of gamma irradiation on MOS devices prepared under different oxidation conditions Is investigated. The C-V characteristics of the devices are studied before and after exposing the latter with gamma radiations of CO⁶⁰ (1.17 and 1.33 MeV gamma rays). For MOS transistor (n-channel depletion type devices) the C-V characteristics change slightly towards the negative voltage axis and the C_min also decreases after Irradiation. For MOS capacitor (wet oxide) there is a change from high frequency C-V characteristics to low frequency C-V characteristics. In the case of a MOS capacitor (HCl grown) breakdown occurs relatively at lower voltage.     

Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC

SCAs(Switched Capacitor Arrays) have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents( 4m A max) and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 m W/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 m V with 625 k Hz full-scale sine wave as input, sampling at 40 MSPS(Mega-samples per Second) and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 m V. The test results validate the feasibility of the MOS capacitor.     

Direct indication of lateral nonuniformities of MOS capacitors from the negative equivalent interface trap density based on charge-temperature technique

The charge-temperature technique was used to investigate the oxide properties of silicon MOS capacitors fabricated on a wafer with an oxide thickness of 660 Å. The stretchout of high frequencyC — V curve of the capacitor after a positive charge-temperature aging was proved to be due to the lateral nonuniformities of mobile charges and the increase of interface traps. The effect of lateral nonuniformitites was found to be successfully described by a model consisting of two parallelly connected nonuniform capacitors. The only parameter of importance is their area ratio, which can be easily determined by theoretical fitting. The appearance of a negative equivalent interface trap density was proposed as a new method to directly identify the existence of lateral nonuniformities.     

Importance of electronic state of two-dimensional electron gas for electron injection process in nano-electronic devices

We report the unexpected temperature dependence of electron tunneling from the two-dimensional electron gas (2DEG) to the Si-dot in a Si-dots floating gate metal-oxide-semiconductor (MOS) capacitor. We indicate that this temperature dependence of the electron tunneling cannot be explained by the conventional one-dimensional tunneling model, and show that it is necessary for a new model which includes the geometrical factor of the system. To extract a mechanism of the electron injection process from the 2DEG to the nano-structure, we have employed the numerical simulation, which includes both the geometrical condition of the system and the experimental setup. We suggest in our new tunneling model that the main contribution to the electron tunneling is induced by the wave-packet-like state of the electron below the Si-dots. We successfully show that the temperature dependence of the electron injection voltage in the Si-dots floating gate MOS capacitor fits our model. This indicates that the spatial distribution of electron density in the two-dimensional electron gas would play a crucial role in the electron tunneling.     

半导体器件总剂量辐射效应的热力学影响

对商用三极管和MOS场效应晶体管进行了不同环境温度下的总剂量辐照实验,对比了不同辐照温度对这两种器件辐射效应特性的影响。实验结果表明,对于同一辐照总剂量,三极管的基极电流、电流增益和MOS场效应晶体管的阈值电压漂移值都随着辐照温度的不同而存在较大的差异。总剂量为100 krad,辐照温度分别为25,70,100 ℃时,NPN三极管的电流增益倍数分别衰减了71,89和113,而NMOS晶体管的阈值电压V_T分别减少了3.53,2.8,2.82 V。