Intermodulation Distortion in CMOS Attenuators and Switches

Gain control elements are widely used in communication systems both to limit the incident power to the circuitry and to control the amplitude of the transmitted signal. Attenuators are one way of controlling the signal amplitude. The distortion performance of common CMOS attenuator topologies is investigated in this work. CMOS device equations that model the device in different regions of operation and which also model short channel effects are used for calculating distortion performance. Calculated distortion is compared with simulation results and experimental data, and qualitative explanations of the distortion curves as well as the deviation between different sources of data are given. Potential improvements in linearity performance of attenuators via circuit design techniques have also been discussed     

CMOS 射频低噪声放大器的设计

讨论了CMOS射频低噪声放大器的相关设计问题,对影响其增益、噪声系数、线性度等性能指标的因素进行了分析,并综述了几种提高其综合性能指标的方法。在此基础上,采用SMIC0．25μm CMOS工艺库,给出了3．8GHz CMOSLNA的设计方案。HSPICE仿真结果表明：电路的功率增益为13．48dB,输入、输出匹配良好,噪声系数为2．9dB,功耗为46．41mw。     

设计RF CMOS蓝牙收发器

使用CMOS RFIC设计2.4GHz蓝牙收发器需要在设计过程中的所有阶段对关键性能进行仔细的验证。这可以通过EDA软件的几个功能来实现,如提供晶片厂模型库,带有蓝牙测试信号的系统兼容性测试模板,还可以和测试仪器的链接,验证仿真数据和实际测量结果是否一致。     

Fast and Automated Electromigration Analysis for CMOS RF PA Design

This paper presents fast and automated electromigration (EM) reliability modeling by using automated modeling generation (AMG) algorithm. The AMG converts human based EM modeling into an automated modeling and simulation process with the help of ANSYS parametric design language (APDL) program. For automating the neural model training process, training-driven adaptive sampling is applied to integrate data generation, data distributions determination, model structure adaptation, training and testing into a unified framework. Fully automated reliability model construction and simulation is achieved for the first time. This method effectively shortens the period of EM modeling by using dynamic sampling method. Furthermore, the heat generation from active devices has been considered to describe the heat effect on the interconnect reliability. Through the proposed technique, the allowable sizes, temperature and output power of a CMOS radio frequency power amplifier (RF PA) are derived to give reliability criteria for PA designer.     

C波段CMOS射频前端电路设计与实现

设计了一款工作在C波段(4.2 GHz)的CMOS射频前端电路,电路包括低噪声放大器和Gilbert型有源双平衡混频器.其中低噪声放大器采用共源和共栅放大器方式,实现了单端输入到差分输出的变换;而混频器的输出端采用电感负载形式.电路采用SMIC 0.18μmRF工艺实现,测试结果表明,混频器的输出频率约为700 MHz,电路的功率增益为24 dB,单边带噪声指数为8 dB,在1.8 V工作电压下,电路总功耗为36 mW.     

Design and optimization of CMOS RF power amplifiers

A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6-μm n-well triple-metal digital CMOS process, and optimized using a simulated-annealing-based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks. A 3-V 85-mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 MHz has been designed, optimized, integrated, and tested     

4·2GHz CMOS射频前端电路设计

设计并实现了一个工作在4.2 GHz的全集成CMOS射频前端电路,包括可实现单端输入到差分输出变换的低噪声放大器和电流注入型Gilbert有源双平衡混频器.电路采用SMIC 0.18 μm RF工艺.测试结果表明,在1.8 V电源电压下,电路的功率增益可达到26 dB,1 dB压缩点为-27 dBm,电路总功耗 (含Buffer) 为21 mA.     

Design of 1.9 GHz RF CMOS VCO

A voltage controlled oscillator (VCO) module is designed, which can be used for the third generation mobile communication (3G) system. The circuit is simulated by spectre radio frequency (RF) by TSMC 0.25 μm CMOS process. During the simulation, the performance parameters of the designed VCO are as follows: tuning range 1.804 GHz-2.039 GHz, phase noise - 136.457 dBc/Hz @1 MHz, - 146.045 dBc/Hz@3 MHz, supply voltage 2.5 V, voltage output rate of 0.8 V-2.6 V, power consumption 25 mW. The layout of the related circuit is drawn by the Virtuoso Layout Editor.     

用于超宽带无线通信系统的CMOS射频混频器的设计

基于射频CMOS集成电路技术,设计出用于超宽带无线通信系统的CMOS下变频器。讨论了利用电容电感网络进行窄带电路阻抗匹配和电阻网络进行宽带电路阻抗匹配的思想和方法。调用SMIC的0．25μm射频工艺库在HSPICE仿真平台上对混频器电路进行了仿真,并对输出信号进行了频谱分析,仿真了该电路的关键技术参数。模拟结果和仿真参数验证了该混频器电路的正确性和可实现性。     

2.1 GHz射频CMOS混频器设计

设计了一个用于第三代移动通信的2.1 GHz CMOS下变频混频器,采用TsMC 0.25 μm CMOS工艺.在设计中,用LC振荡回路作电流源实现低电压;并用增大电流和降低跨导的方法提高线性度.在Cadence RF仿真器中对电路进行了模拟,在1.8 V电源电压下,仿真结果为:1 dB压缩点PtdB-10.65 dBm,lIP3 1.25 dBm,转换增益7 dB,噪声系数10.8 dB,功耗14.4 mW,且输入输出端口实现了良好的阻抗匹配.并用Cadence中的Virtuoso Layout Editor软件绘制了电路的版图.     

Design method for broadband CMOS RF LNA

A design method for a broadband RF CMOS low noise amplifier (LNA) is presented. The shape of the transfer function fits the classical filtering response such as Butterworth or Tchebycheff. This method uses an input matching cell with only parallel LC resonators coupled with admittance inverters realised by series coupling capacitors. An LNA for the 7.2 to 8.6 GHz frequency band designed with this method in a 0.13 /spl mu/m RF CMOS process shows a 3.9 dB noise figure with a voltage gain of 28 dB at 8 GHz with a power consumption of 3.9 mW and a surface consumption of 0.4 mm/sup 2/.     

TD-SCDMA射频前置分频器设计

随着3G的到来,通信系统及通信行业产生了很大的变化,TD-SCDMA作为3G标准之一已开始应用,这使中国在3G发展中有了更多的话语权,一方面可以大幅降低设备的价格,另一方面具有国家安全战略意义.为发展TDSCDMA,需要发展全线的TD产业链,其中射频芯片是一个重要的瓶颈.在TD-SCDMA系统收发信机设计中,将采用零中...     

低功耗CMOS射频低噪声放大器的设计

介绍了一个针对无线通讯应用的2.1 GHz低噪声放大器(LNA)的设计.该电路采用Chartered 0.25 μm CMOS工艺,电源电压为2.5 V,设计中使用了多个电感,详述了设计过程并给出了优化仿真结果. 模拟结果显示,该电路能提供21.63 dB的正向增益(S21),功耗为12.5 mW,噪声系数为2.1 dB,1 dB压缩点为-19.054 1 dBm.芯片面积为0.8 mm×0.6 mm.测试结果达到了设计指标,一致性良好.     

Design of CMOS VHF/RF Biquadratic Filters

In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal G _m-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.     

基于CMOS SOI工艺的射频开关设计

采用0.18μm CMOS SOI工艺技术研制加工的单刀双掷射频开关,集成了开关电路、驱动器和静电保护电路。在DC~6GHz频带内,测得插入损耗0.7dB@2GHz、1dB@4GHz、1.5dB@6GHz,隔离度37dB@2GHz、31dB@4GHz、27dB@6GHz,在5GHz以内端口输入输出驻波比≤1.5:1,输入功率1dB压缩点达到33dBm,IP3达到42dBm。可应用于移动通信系统。     

Design method for fully integrated CMOS RF LNA

An efficient method for fully integrated RF CMOS LNA design is presented. A particular input matching topology enables inductor values to be selected in order to be integrated fully and to minimise the input losses. Moreover, an active device sizing method is used to achieve a 50 /spl Omega/ input impedance with a low noise factor. Simulations show a 3.0 dB noise figure at 2.45 GHz for a power consumption of 10 mW in a 0.28 /spl mu/m RF CMOS process.     

A New Low Voltage RF CMOS Mixer Design

A new architecture of CMOS low voltage downconversion mixer is presented.With 1.452GHz LO input and 1.45GHz RF input,simulation results show that the conversion gain is 15dB,IIP3 is －4.5dBm,NF is 17dB,the maximum transient power dissipation is 9.3mW，and DC power dissipation is 9.2mW.The mixer’s noise and linearity analyses are also presented.     

一种新的射频CMOS混频器结构

提出了一种低电压高增益CMOS下变频混频器的新结构.这个结构避免了堆叠晶体管,因此可以在低电压下工作.在LO信号的频率为1.452GHz,RF信号频率为1.45GHz的情况下,仿真结果表明:混频器的增益为15dB,ⅡP3为-4.5dBm,NF为17dB,最大瞬态功耗为9.3mW,直流功耗为9.2mW.并对该混频器的噪声特性和线性度进行了分析.     

Analysis and design of a low-voltage RF CMOS mixer

A CMOS low-voltage downconversion mixer is presented. With 1.69-GHz local oscillator signal input and 1.63-GHz RF signal input, measurement results show that the conversion gain is 6.631 dB, input-referred third-order intercept point is 1.51 dBm, single-sideband noise figure is 21.43 dB with a 1.8-V supply voltage. The mixer's noise and linearity analysis, layout technique to maximize RF performance and minimize noise performance are also presented in this paper.