Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III–V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t_epi) and height of source region (H_source) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I_on) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (V_t) of 0.1 V, current gain cut-off frequency (f_T) of 12 GHz, and maximum oscillation frequency (f_max) of 283 GHz.     

Characteristics of cylindrical surrounding-gate GaAs_xSb_(1-x)/In_yGa_(1-y)As heterojunction tunneling field-effect transistors

A Ⅲ-Ⅴ heterojunction tunneling field-effect transistor(TFET) can enhance the on-state current effectively,and GaAs_xSb_1_x/In_yGa_1_yAs heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition.In this paper,the performance of the cylindrical surrounding-gate GaAs_xSb_1_x/In_yGa_1_yAs heterojunction TFET with gate-drain underlap is investigated by numerical simulation.We validate that reducing drain doping concentration and increasing gate-drain underlap could be effective ways to reduce the off-state current and subthreshold swing(SS),while increasing source doping concentration and adjusting the composition of GaAs_xSb_1_xIn_yGa_1_yAs can improve the on-state current.In addition,the resonant TFET based on GaAs_xSb_1_x/In_yGa_1_yAs is also studied,and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current,respectively,and is much superior to the conventional TFET.     

隧道场效应晶体管静电放电冲击特性研究

随着器件尺寸的不断减小,集成度的逐步提高,功耗成为了制约集成电路产业界发展的主要问题之一.由于通过引入带带隧穿机理可以实现更小的亚阈值斜率,隧道场效应晶体管(TFET)器件已成为下一代集成电路的最具竞争力的备选器件之一.但是TFET器件更薄的栅氧化层、更短的沟道长度容易使器件局部产生高的电流密度、电场密度和热量,使得其更容易遭受静电放电(ESD)冲击损伤.此外,TFET器件基于带带隧穿机理的全新工作原理也使得其ESD保护设计面临更多挑战.本文采用传输线脉冲的ESD测试方法深入分析了基本TFET器件在ESD冲击下器件开启、维持、泄放和击穿等过程的电流特性和工作机理.在此基础之上,给出了一种改进型TFET抗ESD冲击器件,通过在源端增加N型高掺杂区,有效的调节接触势垒形状,降低隧穿结的宽度,从而获得更好的ESD设计窗口.     

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

Vertical polarization-induced doping InN/InGaN heterojunction tunnel FET with hetero T-shaped gate

A novel vertical InN/InGaN heterojunction tunnel FET with hetero T-shaped gate as well as polarization-doped source and drain region (InN-Hetero-TG-TFET) is proposed and investigated by Silvaco-Atlas simulations for the first time. Compared with the conventional physical doping TFET devices, the proposed device can realize the P-type source and N-type drain region by means of the polarization effect near the top InN/InGaN and bottom InGaN/InN heterojunctions respectively, which could provide an effective solution of random dopant fluctuation (RDF) and the related problems about the high thermal budget and expensive annealing techniques due to ion-implantation physical doping. Besides, due to the hetero T-shaped gate, the improvement of the on-state performance can be achieved in the proposed device. The simulations of the device proposed here in this work show I_ON of 4.45×10^-5 A/μm, I_ON/I_OFF ratio of 10¹³, and SS_avg of 7.5 mV/dec in InN-Hetero-TG-TFET, which are better than the counterparts of the device with a homo T-shaped gate (InN-Homo-TG-TFET) and our reported lateral polarization-induced InN-based TFET (PI-InN-TFET). These results can provide useful reference for further developing the TFETs without physical doping process in low power electronics applications.     

Characteristic enhancement in tunnel field-effect transistors via introduction of vertical graded source

A novel vertical graded source tunnel field-effect transistor(VGS-TFET) is proposed to improve device performance.By introducing a source with linearly graded component, the on-state current increases by more than two decades higher than that of the conventional Ga As TFETs without sacrificing the subthreshold swing(SS) due to the improved band-toband tunneling efficiency. Compared with the conventional TFETs, much larger drive current range can be achieved by the proposed VGS-TFET with SS below the thermionic limitation of 60 m V/dec. Furthermore, the minimum SS about 20 m V/dec indicates its promising potential for further ultralow power applications.     

Symmetric tunnel field-effect transistor (S-TFET)

A novel heterojunction symmetric tunnel field-effect transistor (S-TFET) has been proposed and investigated, for the first time, in order to address the inborn technical challenges of the conventional p-i-n TFET (i.e., asymmetric TFET). With a band-to-band tunneling process between the germanium source/drain region and the silicon channel region, the theoretical limit of the subthreshold slope (SS) can be overcome (i.e., SS ∼ 45 mV/decade). The bidirectional current flow in the S-TFET is implemented with a p-n-p structure. And better performance in the S-TFET is achieved with a thin silicon-pad layer below the source/drain regions. The effects of source/drain/channel doping concentration and thickness on the performance of the device are investigated in order to create an S-TFET design guideline. In the future, the S-TFET will be one of the promising device structures for ultra-low-power applications, especially in integrated circuits that operate with a half-volt power supply voltage.     

Double-gate-all-around tunnel field-effect transistor

In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

MoS2/Si tunnel diodes based on comprehensive transfer technique

Due to the pristine interface of the 2D/3D face-tunneling heterostructure with an ultra-sharp doping profile, the 2D/3D tunneling field-effect transistor (TFET) is considered as one of the most promising low-power devices that can simultaneously obtain low off-state current (I_OFF), high on-state current (I_ON) and steep subthreshold swing (SS). As a key element for the 2D/3D TFET, the intensive exploration of the tunnel diode based on the 2D/3D heterostructure is in urgent need. The transfer technique composed of the exfoliation and the release process is currently the most common approach to fabricating the 2D/3D heterostructures. However, the well-established transfer technique of the 2D materials is still unavailable. Only a small part of the irregular films can usually be obtained by mechanical exfoliation, while the choice of the chemical exfoliation may lead to the contamination of the 2D material films by the ions in the chemical etchants. Moreover, the deformation of the 2D material in the transfer process due to its soft nature also leads to the nonuniformity of the transferred film, which is one of the main reasons for the presence of the wrinkles and the stacks in the transferred film. Thus, the large-scale fabrication of the high-quality 2D/3D tunnel diodes is limited. In this article, a comprehensive transfer technique that can mend up the shortages mentioned above with the aid of the water and the thermal release tape (TRT) is proposed. Based on the method we proposed, the MoS₂/Si tunnel diode is experimentally demonstrated and the transferred monolayer MoS₂ film with the relatively high crystal quality is confirmed by atomic force microscopy (AFM), scanning electron microscopy (SEM), and Raman characterizations. Besides, the prominent negative differential resistance (NDR) effect is observed at room temperature, which verifies the relatively high quality of the MoS₂/Si heterojunction. The bilayer MoS₂/Si tunnel diode is also experimentally fabricated by repeating the transfer process we proposed, followed by the specific analysis of the electrical characteristics. This study shows the advantages of the transfer technique we proposed and indicates the great application foreground of the fabricated 2D/3D heterostructure for ultralow-power tunneling devices.     

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Trap-assisted tunneling(TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor(TFET). In this paper, we assess subthreshold performance of double gate TFET(DG-TFET) through a band-to-band tunneling(BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile(D_(it)) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current.     

DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

A C-shaped pocket tunnel field effect transistor (CSP-TFET) has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance. A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability. The effects of the pocket length, pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs. The DC and analog/RF performance such as on-state current (I_on), on/off current ratio (I_on/I_off), subthreshold swing (SS) transconductance (g_m), cut-off frequency (f_T) and gain-bandwidth product (GBP) are investigated. The optimized CSPTFET device exhibits excellent performance with high I_on (9.98×10 ^{- 4} A/μm), high I_on/I_off (～ 10¹¹), as well as low SS (～ 12 mV/dec). The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.     

Two-dimensional threshold voltage model of nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor (TFET) is a potential candidate for the post-CMOS era. In this paper, a threshold voltage model is developed for this new kind of device. First, two-dimensional (2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions. Then based on the physical definition of threshold voltage for the nanoscale TFET, the threshold voltage model is developed. The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data. It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper. This threshold voltage model provides a valuable reference to the TFET device design, simulation, and fabrication.     

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor(TFET) is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional(2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.     

Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET

The favorable electrostatic potential and tunneling underneath the overall gate region, which prevents legitimate source to drain tunneling, controllability over the gate is assisted in vertical TFET configurations. An L-TFET (L-shaped Tunneling Field-Effect Transistor) has a larger tunneling length than a veritable TFET. As a consequence, the current in the on-state (I_on) has gotten better. The increased ambipolar current and low I_on/I_off ratio of L-TFET will need to be tuned for low-power and high-frequency functionality. On the other hand, significantly worse switching performance and distortions may lead to a weak robust device. By establishing a high-k gate oxide-based drain underlap region with dual gate, this study is dedicated to ameliorating the I_on/I_off by subverting ambipolar behavior. To investigate the impact of height of second gate (H_gate2) and work-function of this (WF_gate2), EBD (Energy Band Diagram), electric field distribution in X and Y direction, potential and recombination rate are examined under various conditions. Which leads to enhanced DC/RF and linearity performance. Along with this, Current-Voltage characteristics, DC/RF, and linearity performance Figure of Merits (FOMs) also investigated the assessment of variation of H_gate2 and WF_gate2, and it is optimized for the better suppression of I_ambi (ambipolar current) with a steep slope in transfer characteristics. In addition to that, Current-voltage statistics (I_ds − V_gs), DC/RF, and linearity efficiency FOMs were being used to assess the influence of changing the H_gate2 and WF_gate2, which was modulated for greater I_ambi suppression (ambipolar current) with improved SS and V_th for the proposed device.     

高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD) SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

Novel carbon nanotube field effect transistor with graded double halo channel

A novel carbon nanotube field effect transistor with symmetric graded double halo channel (GDH–CNTFET) is presented for suppressing band to band tunneling and improving the device performance. GDH structure includes two symmetric graded haloes which are broadened throughout the channel. The doping concentration of GDH channel is at maximum level at drain/source side and is reduced gradually toward zero at the middle of channel. The doping distribution at source side of channel reduces the drain induced barrier lowering (DIBL) and the drain side suppresses the band to band tunneling effect. In addition, broadening the doping throughout the channel increases the recombination of electrons and holes and acts as an additional factor for improving the band to band tunneling. Simulation results show that applying this structure on CNTFET enhances the device performance. In comparison with double halo structure with equal saturation current, the proposed GDH structure shows better characteristics and short channel parameters. Furthermore, the delay and power delay product (PDP) analysis versus on/off current ratio shows the efficiency of the proposed GDH structure.     

MOSFET scaling into the 10 nm regime

Scaling limits of the double-gate MOSFET structure are explored. Because short-channel effects can be adequately controlled by thinning the silicon body, the eventual scaling limit will be determined by the ability to control off-state leakage due to quantum mechanical tunneling and thermionic emission between the source and drain. Depending on threshold voltage and the source/drain doping profile, this will restrict gate length scaling to 5–11 nm. As power supplies are scaled down, maintaining on-state drive current may become difficult due to threshold voltage limitations. Series resistance becomes important as the body thickness is reduced, but intrinsic device performance may still be improved.     

Improved performance of 4H-SiC metal-semiconductor field-effect transistors with step p-buffer layer

An improved 4H-SiC metal-semiconductor field-effect transistors (MESFETs) with step p-buffer layer is proposed, and the static and dynamic electrical performances are analysed in this paper. A step p-buffer layer has been applied not only to increase the channel current, but also to improve the transconductance. This is due to the fact that the variation in p-buffer layer depth leads to the decrease in parasitic series resistance resulting from the change in the active channel thickness and modulation in the electric field distribution inside the channel. Detailed numerical simulations demonstrate that the saturation drain current and the maximum theoretical output power density of the proposed structure are about 30% and 37% larger than those of the conventional structure. The cut-off frequency and the maximum oscillation frequency of the proposed MESFETs are 14.5 and 62 GHz, respectively, which are higher than that of the conventional structure. Therefore, the 4H-SiC MESFETs with step p-buffer layer have superior direct-current and radio-frequency performances compared to the similar devices based on the conventional structure.     

New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor (4H-SiC MESFET) structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications. The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one- and two-dimensional Poisson's equations. In the models, we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted. The direct-current and the alternating-current performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 μ m are calculated. The calculated results are in good agreement with the experimental data. The current is larger than that of the conventional structure. The cutoff frequency (f_T) and the maximum oscillation frequency (f_max) are 20.4 GHz and 101.6 GHz, respectively, which are higher than 7.8 GHz and 45.3 GHz of the conventional structure. Therefore, the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.