一种高速高增益CMOS运算放大器的设计

设计了一种应用于采样保持电路中高速高增益运算放大器。该运放采用全差分增益提高型共源共栅结构。在输入信号通路上加入适当的补偿电容,消除了零极点对对运放建立时间的影响,同时对主运放的次极点进行了优化,改进了相位裕度。采用0.35μmCMOS工艺仿真,结果表明,运放的开环直流增益达到106dB,单位带宽为831MHz（负载电容8pF）,相位裕度为60.5°,压摆率为586V/μs,满足12位50MS/s流水线ADC中采样保持电路性能要求。     

Low‐Voltage CMOS Current Feedback Operational Amplifier and Its Application

A novel low‐voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail‐to‐rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ±0.75 V with a total standby current of 304 µA. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ±1 mA. An application of the CFOA to realize a new all‐pass filter is given. PSpice simulation results using 0.25 µm CMOS technology parameters for the proposed CFOA and its application are given.     

一种30 dB增益范围的CMOS可变增益放大器

采用0.25μm CMOS工艺设计了一种增益动态范围为30dB的可变增益放大器.该可变增益放大器以Gilbert单元为主体电路,在此基础上采用共源共栅结构,以及电流-电压负反馈的形式,极大地提高了电路的放大增益,并采用共模反馈回路,稳定了高阻输出节点的共模电压,还加入了指数控制电路,使增益与控制电压成dB-线性变化.电源工作电压3.3 V,电路功耗15 mW.     

A 1.2 V 12 b 60 MS/s CMOS Analog Front‐End for Image Signal Processing Applications

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front‐end (AFE) employing low‐power and flexible design techniques for image signal processing. An op‐amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog‐to‐digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 µm CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal‐to‐noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 mm² and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.     

一种dB线性数字控制可变增益放大器的设计

设计了一种dB线性增益的数字控制可变增益放大器。以二极管做负载的全差分输入共源极放大器为原型,通过同时同比例地改变输入输出晶体管尺寸比和偏置电流比来控制增益变化,使输入输出晶体管的电流密度保持一恒定值,提高了电路在低增益时的线性度。电路采用NEC 0.35μm CMOS标准工艺库进行设计。仿真结果表明,dB线性增益范围为-11.85dB到11.64dB,增益误差小于0.5dB。增益为-11.85dB时,其1-dB压缩点达到8.35dBm,-3dB增益带宽大于62MHz,并且随设定的增益值在62MHz和240MHz之间变化。     

一种具有温度补偿的宽带CMOS可变增益放大器

设计实现了一个具有温度补偿的宽带CMOS可变增益放大器,该可变增益放大器的核心电路由三级基于改进型Cherry-Hooper结构的可变增益单元级联而成,并通过一种温度系数增强的且可编程的偏置电路和增益控制电路对可变增益放大器的增益进行温度补偿。采用中芯国际0.13μm CMOS工艺流片,测试结果表明可变增益放大器的可变增益范围为-13～27dB,经过温度补偿后,在相同增益控制电压下其增益在0～75°C温度范围内的变化范围不超过3dB。可变增益放大器的3dB带宽为0.8～3GHz,输入1dB压缩点为-50～-21dBm,在1.2V电压下,功耗为21.6mW。     

一种带增益提高技术的高增益CMOS运算放大器的设计

给出了一种用在高速高精度流水线型模数转换器中的具有高增益和高单位增益频率的全差动CMOS运算放大器的设计,电路结构主要采用折叠式共源共栅结构,并采用增益提高技术提高放大器的增益。共模反馈电路由开关电容共模反馈电路实现。模拟结果显示,其开环直流增益可达到106 dB,在负载电容为2 pF时单位增益频率达到了167 MHz,满足了对模数转换器的高速度和高精度的要求。     

基于衬底运放的2阶温度补偿带隙基准电路

采用TSMC 0.25μm CMOS工艺,提出了一种基于衬底驱动放大器的高精度带隙基准(BGR)电路。采用衬底驱动技术的放大器,有效地降低了电源电压;通过PTAT2电流产生电路对基准电路进行2阶温度补偿,有效地降低了输出基准电压的温度系数;采用改进型共源共栅输出级电路,很好地改善了电路的电源抑制比(PSRR)。HSPICE仿真结果显示:在2 V供电电压下,输出基准电压为1.261 V,温度系数为8.24×10-6/℃,低频电源抑制比-为91 dB。整体电路功耗为1.37 mW。     

Integrated Rail‐to‐Rail Low‐Voltage Low‐Power Enhanced DC‐Gain Fully Differential Operational Transconductance Amplifier

In this paper, we present an integrated rail‐to‐rail fully differential operational transconductance amplifier (OTA) working at low‐supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand‐by power dissipation (lower than 0.17 mW in the rail‐to‐rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 μm), presents a 37 V/μs slew‐rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.     

一种指数增益控制宽范围可变增益放大器

采用中芯国际(SMIC)0.18μm CMOS工艺设计了一种具有指数增益特性的的宽增益调节范围的可变增益放大器,该放大器由Gilbert单元、指数电压转换电路、直流消除电路及超级源级跟随器组成。经过Cadence仿真验证,该放大器可以实现-11.14dB~30.39dB的增益连续变化,其-3dB带宽为250MHz,控制电压与增益成dB线性关系。     

一种采用增益增强技术的全差分运放设计和实现

设计了一种采用增益增强技术并带有共模反馈的全差分运算放大器.该运算放大器主要由三个折叠式共源共栅结构的运放、一个偏置电路和一个共模反馈电路组成.运算放大器采用chartered 0.35 μm CMOS工艺实现,仿真结果表明运放开环增益为106.8 dB,单位增益带宽为58 MHz,相位裕度为79°(负载Cload=1 pF).对流片运放进行测试和分析,运算放大器测试指标和仿真指标基本接近,较好达到预先的设计要求.     

恒电压增益的低电压Rail—to—Rail运算放大器

基于 Alcatel的 0 .3 5μm标准 CMOS工艺 (VT=0 .6 5 V) ,模拟实现了工作电压低达 1 .8V、电压增益偏差仅为 3 % (整个输入共模偏置电压范围内 )的运算放大器 ;电路的设计也避免了差分输入对中 PMOS管和 NMOS管的 W/L的严格匹配 ,增强了电路对工艺的坚固性。对输入差分对偏置电流的控制电路、差分输入对的有源负载和 AB类 Rail- to- Rail输出级进行了整体考虑 ,确保电压增益恒定的新型结构 ,使该运放在 2 V电源电压下 ,电压增益达到 80 d B(1 0 kΩ 电阻和 1 0p F电容并联负载 ) ,单位增益带宽为 1 2 MHz,相位裕量 72°     

A Power‐Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two‐stage power‐efficient class‐AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low‐power dissipation and low‐voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class‐AB amplifier. The design is fabricated using 0.18‐μm CMOS technology.     

Realization of n‐th Order Voltage Transfer Function Using a Single Operational Transresistance Amplifier

4 new configuration to realize the most general n‐th order voltage transfer function is proposed. It employs only one operational transresistance amplifier (OTRA) as the active element. In the synthesis of the transfer function, the RC:–RC decomposition technique is used. To the best of the author's knowledge, this is the first topology to be used in the realization of an n‐th order transfer function employing a single OTRA.     

Ultra‐small Form‐Factor Helix on Pad‐Type Stage‐Bypass WCDMA Tx Power Amplifier Using a Chip‐Stacking Technique and a Multilayer Substrate

A fully integrated small form‐factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix‐on‐pad integrated passive device output matching, a chip‐stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm × 2.2 mm. A stage‐bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.     

High‐Gain Wideband CMOS Low Noise Amplifier with Two‐Stage Cascode and Simplified Chebyshev Filter

An ultra‐wideband low‐noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18‐μm CMOS process and adopts a two‐stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input‐impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power‐gain bandwidth product of 399.4 GHz.     

Rule‐Based Anomaly Detection Technique Using Roaming Honeypots for Wireless Sensor Networks

Because the nodes in a wireless sensor network (WSN) are mobile and the network is highly dynamic, monitoring every node at all times is impractical. As a result, an intruder can attack the network easily, thus impairing the system. Hence, detecting anomalies in the network is very essential for handling efficient and safe communication. To overcome these issues, in this paper, we propose a rule‐based anomaly detection technique using roaming honeypots. Initially, the honeypots are deployed in such a way that all nodes in the network are covered by at least one honeypot. Honeypots check every new connection by letting the centralized administrator collect the information regarding the new connection by slowing down the communication with the new node. Certain pre‐defined rules are applied on the new node to make a decision regarding the anomality of the node. When the timer value of each honeypot expires, other sensor nodes are appointed as honeypots. Owing to this honeypot rotation, the intruder will not be able to track a honeypot to impair the network. Simulation results show that this technique can efficiently handle the anomaly detection in a WSN.     

Robust power control for IEEE 802.15.4 wireless sensor networks with round‐trip time‐delay uncertainty

This paper presents a novel, practically implementable robust Power Control (PC) technique that is generally applicable to a variety of IEEE 802.15.4 infrastructure and peer‐to‐peer wireless sensor networks (WSNs) where there is a round‐trip time‐delay uncertainty. In this methodology, robust stability and performance constraints are cast as a set of exclusion regions on the Nichols chart. The desired PC strategy is achieved through an iterative shaping of the system frequency response until these constraints are satisfied. A Smith Predictor (SP) is also adopted to mitigate the effects of time delay that occurs quite naturally in this type of problem. Such an approach is shown to be entirely appropriate for the discrete time controller design problem at hand. The designs are validated experimentally using a fully compliant 802.15.4 testbed where mobility is introduced using autonomous robots. This testbed provides a good basis for a formal comparison of the new approach against a number of existing strategies. Copyright © 2009 John Wiley & Sons, Ltd.     

Accurate Tunable‐Gain 1/x Circuit Using Capacitor Charging Scheme

This paper proposes an accurate tunable‐gain 1/x circuit. The output voltage of the 1/x circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/x circuit is tuned by a 10‐bit digital code. The 1/x circuit was fabricated using a 0.18 μm CMOS process. Its core area is , and it consumes 278 μW at and . Its error is within 1.7% at to 1 V.     

Enhanced‐Gain Planar Substrate‐Integrated Waveguide Cavity‐Backed Slot Antenna with Rectangular Slot Window on Superstrate

A novel substrate‐integrated waveguide (SIW) cavity‐backed slot antenna is proposed in this study to achieve enhanced‐gain performance. The peak gain is remarkably improved with the use of an SIW cavity and metallic superstrate. The superstrate comprises a single rectangular slot window and two half‐wavelength patches. The gain can be enhanced by combining the in‐phase radiating fields. Further, the 10 dB bandwidth of the proposed antenna ranges from 2.32 GHz to 2.49 GHz, which covers the wireless local area network band. The measured peak gain is 9.44 dBi at 2.42 GHz.