III-V field-effect transistors for low power digital logic applications

Sustaining Moore’s Law of doubling CMOS transistor density every twenty four months will require not only shrinking the transistor dimensions, but also introduction of new materials and new device architectures to achieve the highest performance per watt of power dissipation. Compound semiconductor-based quantum-well field effect transistors have recently emerged as a promising transistor option for future ultra low-power logic applications. This paper reviews the opportunities and challenges in this exciting field of research.     

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

Current-mode cyclic ADC for low power and high speed applications

A new current-mode cyclic ADC is proposed. An 8 bit ADC is fabricated and fully tested. The experimental results are summarised and compared with other schemes. This ADC enables a conversion time less than 10 mu s with clock frequency of 450 kHz to be obtained. The proposed ADC is found to be useful where the power and size are crucial requirements.<>     

Ultralinear UHF power transistors for CATV applications

An investigation of the cross-modulation performance of UHF power transistors and its correlation with the gain parameter curves S21(IC, VCB) shows that such transistors today exhibit an inherent linearity limitation and are not optimized for ultralinear applications. This means that using higher power transistors does not result in a larger output signal with low cross-modulation distortion. Presented measurements clearly demonstrate that the nonlinear products increase, not only with increasing emitter dc current, but also with collector voltage above certain limiting values ICLand VCL, respectively; ICLand VCLare relatively small compared with the corresponding maximum permissible values of ICand VCB. Their existence can be explained by current crowding effects, by the space-charge limitation of the collector current, by the nonuniform thermal conductance, by the temperature gradients, and by the unequal current density distribution across the (large) active areas of power transistors. A correlation between the VCgain parameter falloff effect and the "thermal distortions," has been established. Design and selection criteria for ultralinear transistors needed in CATV amplifers are given. A simple linearity test method is described.     

High performance low temperature metal-induced unilaterallycrystallized polycrystalline silicon thin film transistors forsystem-on-panel applications

Thin film transistors (TFTs) with low-temperature processed metal-induced laterally crystallized (MILC) channels and self-aligned metal-induction crystallized (MIC) source and drain regions have been demonstrated recently as potential devices for realizing electronics on large-area, inexpensive glass panels. While these TFTs are better than their solid-phase crystallized counterparts in many device performance measures, they suffer from higher off-state leakage current and early drain breakdown. A new technology is proposed, employing metal-induced-unilateral crystallization (MIUC), which results in the removal from the edges of and within the channel region all major grain boundaries transverse to the drain current flow. Compared to the conventional “bilateral” MILC TFTs, the new MIUC devices are shown to have higher field-effect mobility, significantly reduced leakage current, better immunity to early drain breakdown, and much improved spatial uniformity of the device parameters. Thus they are particularly suitable for realizing low temperature CMOS systems on inexpensive glass panels     

Performance analysis of InSb based QWFET for ultra high speed applications

An indium antimonide based QWFET (quantum well field effect transistor) with the gate length down to 50 nm has been designed and investigated for the first time for L-band radar applications at 230 GHz. QWFETs are designed at the high performance node of the International Technology Road Map for Semiconductors (ITRS) requirements of drive current (Semiconductor Industry Association 2010). The performance of the device is investigated using the SYNOPSYS CAD (TCAD) software. InSb based QWFET could be a promising device technology for very low power and ultra-high speed performance with 5-10 times low DC power dissipation.     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay     

High power and low optical feedback noise AlGaAs single quantum well lasers

GaAs-AlGaAs single quantum well self-aligned lasers have been developed for optical disc recording. The lasers emitting at 834 nm have realised low optical feedback noise as well as high output power. The lasers have shown less than -130 dB/Hz relative intensity noise at 3 mW, and stable 50 mW operation (over 500 hours at 50 degrees C ambient).<>     

低空超高速运动平台测高算法

针对传统线性调频连续波雷达在低空超高速运动平台的高度测量中高度表会受多普勒徙动和距离徙动影响的问题,提出了一种脉冲频移调频体制的发射波形,利用回波特性抵消多普勒徙动和距离徙动,结合移位能量归一化变换(Shift Normalized Energy Transform, SNET)自适应测高算法,在满足系统测高精度的前提下大大提高了计算效率,满足系统实时性要求。软件仿真证明了所提的发射波形和算法的正确性。     

InSb quantum dot LEDs grown by molecular beam epitaxy for mid-infrared applications

We report the molecular beam epitaxial growth of InSb quantum dots (QD) inserted as sub-monolayers in an InAs matrix which exhibit intense mid-infrared photoluminescence up to room temperature. The InSb QD sheets were formed by briefly exposing the surface to an antimony flux (Sb₂) exploiting an As-Sb anion exchange reaction. Light emitting diodes were fabricated using 10 InSb QD sheets and were found to exhibit bright electroluminescence with a single peak at 3.8 μm at room temperature.     

Technology mapping for low power in logic synthesis

Traditionally, three metrics have been used to evaluate the quality of logic circuits - size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of this research, we have today very powerful techniques for synthesis targeting area and testability; and to a lesser extent, circuit speed. The last couple of years have seen the addition of another dimension in the evaluation of circuit quality - its power requirements. Low-power circuits are emerging as an important application domain, and synthesis for low power is demanding attention.

The research presented in this paper addresses one aspect of low-power synthesis. It focuses on the problem of mapping a technology-independent circuit to a technology-specific one, using gates from a given library, with power as the optimization metric. We believe that the difficulty in obtaining accurate models of power at the technology-independent level makes it difficult to optimize for power at this level, and thus feel that the technology mapping step offers the most direct way of power optimization during logic synthesis.

Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically it is observed that a significant variation in the power consumption is possible just by varying the choice of gates selected. In fact, our experiments over a large set of benchmark circuits show that compared to mapping for power, mapping for area or delay can lead to circuits that have significantly higher power consumption: up to 32% higher in case of mapping for area, and up to 153% higher in case of mapping for delay.     

Base diffusion isolated transistors for low power integrated circuits

Base diffusion isolated transistors (BDI) designed for low power, nonsaturating, integrated circuits have been fabricated. Buried collectors are unnecessary in these low power devices, resulting in structures equivalent to discrete transistors in complexity of fabrication. A low-current power supply is required for isolation purposes. Transistor characteristics differ negligibly from those of standard transistors at collector currents <0.05 mA, and are satisfactory for application in linear circuits at currents up to at least 0.1 mA. Transistor fTis 80 MHz at 0.1 mA emitter current, 2 V collector voltage.     

Low power, high speed, charge recycling CMOS threshold logic gate

A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design     

Optimization of silicon bipolar transistors for high current gainat low temperatures

Bipolar transistors designed specifically for operation at liquid-nitrogen (LN₂) temperature are discussed. It is found that for high-gain LN₂ bipolar transistors, the emitter concentration should be around 5×10¹⁸ cm^-3. Compensating impurities in the base should be kept to minimum. Test bipolar transistors with polysilicon emitter contacts were fabricated using these criteria. The devices show very little current degradation between room temperature and 77 k. Polysilicon emitter contacts are also shown to be somewhat more effective at lower temperatures     

Collector design tradeoffs for low voltage applications of advancedbipolar transistors

The values of BV_ceo are computed for transistors with highly doped collectors and with thin reach-through collectors, using various sets of ionization coefficients including new data. Computed values of BV_ceo are compared with experimental results. It is shown that transistors with thin reach-through collectors have higher current capability for any given BV_ceo compared to those with highly doped collectors. Tradeoffs in terms of BV_ceo, maximum collector current and the maximum frequency of operation are studied for transistors with highly doped and thin reach-through collectors     

Circuit activity based logic synthesis for low power reliableoperations

A system developed to synthesize both finite state machines and combinational logic for low-power applications, called SYCLOP, is described. SYCLOP tries to minimize the transition density at the internal nodes of a circuit to minimize power dissipation during normal operation. As input signal probabilities and transition densities are considered during the synthesis process, a particular circuit can be synthesized in different ways for different applications that require different types of inputs. For the present state inputs to the combinational circuit of a state machine, simulation was used to determine the signal probabilities and transition densities. The algorithm is not limited by the number of bits used for state assignment. The multilevel optimization process extracts kernels so that there is a balance between area and power optimization. Results have been obtained for a wide range of MCNC benchmark examples     

Power rail logic: a low power logic style for digital GaAs circuits

This paper describes a new logic style called Power Rail Logic (PRL), which is compatible with direct-coupled FET logic (DCFL) circuits. Multiplexors, latches, flip-flops, and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-b barrel shifters designed in DCFL and in PRL was successfully fabricated and tested. Test results are given for both circuits     

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Powering billions of devices is one of the most challenging barrier in achieving the future vision of IoT. Most of the sensor nodes for IoT based systems depend on battery as their power source and therefore fail to meet the design goals of lifetime power supply, cost, reliable sensing and transmission. Energy harvesting has the potential to supplant batteries and thus prevents frequent battery replacement. However, energy autonomous systems suffer from sudden power variations due to change in external natural sources and results in loss of data. The memory system is a main component which can improve or decrease performance dramatically. The latest versions of many computing system use chip multiprocessor (CMP) with on-chip cache memory organized as array of SRAM cell. In this paper, we outline the challenges involved with the efficient power supply causing power outage in energy autonomous/self-powered systems. Also, various techniques both at circuit level and system level are discussed which ensures reliable operation of IoT device during power failure. We review the emerging non-volatile memories and explore the possibility of integrating STT-MTJ as prospective candidate for low power solution to energy harvesting based IoT applications. An ultra-low power hybrid NV-SRAM cell is designed by integrating MTJ in the conventional 6T SRAM cell. The proposed LP8T2MTJ NV-SRAM cell is then analyzed using multiple key performance parameters including read/write energies, backup/restore energies, access times and noise margins. The proposed LP8T2MTJ cell is compared to conventional 6T SRAM counterpart indicating similar read and write performance. Also, comparison with the existing MTJ based NV-SRAM cells show 51–78% reduction in backup energy and 42–70% reduction in restore energy.