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编码器/解码器专用芯片及其应用 总被引:4,自引:0,他引:4
文章介绍几种主要应用于遥控遥测领域的新型编码器/解码器专用芯片。文中描述了这些芯片的应用特性与方法,并列举了部分应用实例供参考。 相似文献
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编码器MC145026及解码器MC145027/MC145028张兴明许多电子系统中需要远程多路或多点的数据通信和控制操作,采用并行方式,有接线多的缺点;采用多机串行方式,从机串行信号接收电路稍嫌复杂。编码器MC145026和解码器MC145027、... 相似文献
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为了满足数字图像处理系统对高速高分辨率数字图像采集与处理的需求,根据VGA显示的原理,采用Camera Link摄像机和VGA接口,借助DSP和FPGA等大规模集成电路,设计开发一个高速图像采集处理系统,并利用该系统实现了图像的采集、处理与VGA显示。 相似文献
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介绍了用于彩色多频显示器的新型集成电路(WT8045系列)的特点、排列次序表、引脚内容,重点介绍了主要功能应用,如同步信号鉴别、电源节能检波、应用电路,并提出了有关信息指南。 相似文献
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本文介绍了一项专利产品,它是在DVB-ASI接口的MPEG解码器与编码器间实现多模式的复式组合,在DVB-S、DVB- C和T-MMB数字电视地面广播新国标的前端发送平台,以及以SDH为远程传送的传输平台上得到广泛应用,并为第二代信源编码AVS国标的普及预留广阔发展空间,它将为数字电视和数字媒体的基本建设提供一条高效率,低成本的可行方案。 相似文献
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在光码分多址(CDMA)通信中,光延迟线编/解码器是实现全光编/解码的关键技术.本文对并行结构的光纤延迟线编/编码器的原理及构造方法进行了分析,并给出相应的实验结果。 相似文献
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8B/10B编解码的IP核设计 总被引:2,自引:0,他引:2
研究了8B/10B编码的编码特点和内在相关性,并在此基础上介绍了一种用Verilog HDL设计8B/10B编解码逻辑描述的方法,将其嵌入到FPGA中或设计成ASIC,可构成一个资源使用少、速度快、可靠性高的IP核.文中着重介绍8B/10B编解码总体设计方案,详细描述其内部工作原理和实现.最后给出在Altera公司软件平台QuartusⅡ上进行EDA的综合和仿真结果. 相似文献
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Although Low-Density Parity-Check (LDPC) codes perform admirably for large block sizes — being mostly resilient to low levels of channel SNR and errors in channel equalization — real time operation and low computational effort require small and medium sized codes, which tend to be affected by these two factors. For these small to medium codes, a method for designing efficient regular codes is presented and a new technique for reducing the dependency of correct channel equalization, without much change in the inner workings or architecture of existing LDPC decoders is proposed. This goal is achieved by an improved intrinsic Log-Likelihood Ratio (LLR) estimator in the LDPC decoder — the ILE-Decoder, which only uses LDPC decoder-side information gathered during standard LDPC decoding. This information is used to improve the channel parameters estimation, thus improving the reliability of the code correction, while reducing the number of required iterations for a successful decoding. Methods for fast encoding and decoding of LDPC codes are presented, highlighting the importance of assuring low encoding/decoding latency with maintaining high throughput. The assumptions and rules that govern the estimation process via subcarrier corrected-bit accounting are presented, and the Bayesian inference estimation process is detailed. This scheme is suitable for application to multicarrier communications, such as OFDM. Simulation results in a PLC-like environment that confirm the good performance of the proposed LDPC coder/decoder are presented. 相似文献
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Direct-sequence optical code-division multiple-access (DS-OCDMA) encoder/decoder based on sampled fiber Bragg gratings (S-FBGs) is characterized using phase-sensitive optical low-coherence reflectometry (OLCR). The OLCR technique allows localized measurements of FBG wavelength and physical length inside one S-FBG. This paper shows how the discrepancies between specifications and measurements of the different FBGs have some impact on spectral and temporal pulse responses of the OCDMA encoder/decoder. The FBG physical lengths lower than the specified ones are shown to affect the mean optical power reflected by the OCDMA encoder/decoder. The FBG wavelengths that are detuned from each other induce some modulations of S-FBG reflectivity resulting in encoder/decoder sensitivity to laser wavelength drift of the OCDMA system. Finally, highlighted by this OLCR study, some solutions to overcome limitations in performance with the S-FBG technology are suggested. 相似文献
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Hasegawa K. Ohara K. Oka A. Kamada T. Nagaoka Y. Yano K. Yamauchi E. Kashiro T. Nakagawa T. 《Solid-State Circuits, IEEE Journal of》1996,31(11):1780-1788
This paper describes the realization of a video encoder/decoder chip set for the consumer use digital video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 digital component video signal into the standard-definition digital VCR (DV) format or decode the DV format signal into a component video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-μm 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-μm CMOS technology, contains about 500 k transistors on 71 mm2 and 79 mm2 die, respectively 相似文献
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采用光纤光栅编/解码器的FFH-OCDMA实验系统 总被引:1,自引:1,他引:0
着重介绍了采用光纤光栅编/解码器的FFH—OCDMA实验系统的设计以及整个系统的结构,简要分析了系统的多用户干扰和地址码选择等,最后通过实验平台,验证了光纤光栅编/解码器和整个系统的性能。 相似文献